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17 lines
300 B
Verilog
17 lines
300 B
Verilog
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// Model for tristate bus on altera
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// FIXME do we really need to use a megacell for this?
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module bustri (data,
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enabledt,
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tridata);
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input [15:0] data;
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input enabledt;
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inout [15:0] tridata;
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assign tridata = enabledt ? data :16'bz;
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endmodule // bustri
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