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78 lines
2.5 KiB
Text
78 lines
2.5 KiB
Text
########################################################################
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## Welcome to the USRP FPGA source code tree
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########################################################################
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usrp1/
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Description: generation 1 products
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Devices: USRP classic only
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Tools: Quartus from Altera
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Project file: usrp1/toplevel/usrp_std/
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usrp2/
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Description: generation 2 products
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Devices: USRP2, N2XX, B100, E1XX
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Tools: ISE from Xilinx, GNU make
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Build Instructions:
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1) ensure that xtclsh is in the $PATH
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2) cd usrp2/top/<project-directory>
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3) make -f Makefile.<device> bin
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4) bin file in build-<device>/*.bin
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########################################################################
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## Customizing the DSP
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########################################################################
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As part of the USRP FPGA build-framework,
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there are several convenient places for users to insert
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custom DSP modules into the transmit and receive chains.
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* before the DDC module
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* after the DDC module
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* replace the DDC module
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* before the DUC module
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* after the DUC module
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* replace of the DUC module
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* as an RX packet engine
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* as an TX packet engine
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Customizing the top level makefile
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Each USRP device has a makefile associated with it.
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This makefile contains all of the necessary build rules.
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When making a customized FPGA design,
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start by copying the current makefile for your device.
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Makefiles can be found in the usrp2/top/<dir>/Makefile.*
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Edit your new makefile:
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* set BUILD_DIR to a unique directory name
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* set CUSTOM_SRCS for your verilog sources
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* set CUSTOM_DEFS (see section below)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Inserting custom modules
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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CUSTOM_DEFS is a string of space-separate key-value pairs.
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Set the CUSTOM_DEFS variable so the FPGA fabric glue
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will substitute your custom modules into the DSP chain.
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Example:
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CUSTOM_DEFS = "TX_ENG0_MODULE=my_tx_engine RX_ENG0_MODULE=my_rx_engine"
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Where my_tx_engine and my_rx_engine are the names of custom verilog modules.
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The following module definition keys are possible (X is a DSP number):
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* TX_ENG<X>_MODULE: set the module for the transmit chain engine.
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* RX_ENG<X>_MODULE: set the module for the receive chain engine.
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* RX_DSP<X>_MODULE: set the module for the transmit dsp chain.
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* TX_DSP<X>_MODULE: set the module for the receive dsp chain.
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Examples of custom modules can be found in usrp2/custom/*.v
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