mirror of
https://github.com/saymrwulf/uhd.git
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d71344091b
today we added shutoff the DAC when not transmitting using EOB as an indicator added various other features and cleaned up code for soft time control
449 lines
16 KiB
C++
449 lines
16 KiB
C++
//
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// Copyright 2010-2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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#include "codec_ctrl.hpp"
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#include "usrp_commands.h"
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#include "clock_ctrl.hpp"
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#include "ad9862_regs.hpp"
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#include <uhd/types/dict.hpp>
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#include <uhd/utils/assert.hpp>
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#include <uhd/utils/algorithm.hpp>
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#include <uhd/utils/byteswap.hpp>
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#include <boost/cstdint.hpp>
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#include <boost/format.hpp>
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#include <boost/tuple/tuple.hpp>
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#include <boost/math/special_functions/round.hpp>
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#include <boost/assign/list_of.hpp>
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#include <iostream>
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#include <iomanip>
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using namespace uhd;
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static const bool codec_debug = false;
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const gain_range_t usrp1_codec_ctrl::tx_pga_gain_range(-20, 0, double(0.1));
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const gain_range_t usrp1_codec_ctrl::rx_pga_gain_range(0, 20, 1);
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/***********************************************************************
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* Codec Control Implementation
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**********************************************************************/
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class usrp1_codec_ctrl_impl : public usrp1_codec_ctrl {
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public:
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//structors
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usrp1_codec_ctrl_impl(usrp1_iface::sptr iface,
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usrp1_clock_ctrl::sptr clock,
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int spi_slave);
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~usrp1_codec_ctrl_impl(void);
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//aux adc and dac control
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double read_aux_adc(aux_adc_t which);
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void write_aux_dac(aux_dac_t which, double volts);
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//duc control
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void set_duc_freq(double freq);
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void enable_tx_digital(bool enb);
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//pga gain control
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void set_tx_pga_gain(double);
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double get_tx_pga_gain(void);
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void set_rx_pga_gain(double, char);
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double get_rx_pga_gain(char);
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//rx adc buffer control
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void bypass_adc_buffers(bool bypass);
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private:
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usrp1_iface::sptr _iface;
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usrp1_clock_ctrl::sptr _clock_ctrl;
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int _spi_slave;
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ad9862_regs_t _ad9862_regs;
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aux_adc_t _last_aux_adc_a, _last_aux_adc_b;
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void send_reg(boost::uint8_t addr);
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void recv_reg(boost::uint8_t addr);
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double coarse_tune(double codec_rate, double freq);
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double fine_tune(double codec_rate, double freq);
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};
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/***********************************************************************
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* Codec Control Structors
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**********************************************************************/
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usrp1_codec_ctrl_impl::usrp1_codec_ctrl_impl(usrp1_iface::sptr iface,
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usrp1_clock_ctrl::sptr clock,
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int spi_slave)
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{
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_iface = iface;
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_clock_ctrl = clock;
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_spi_slave = spi_slave;
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//soft reset
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_ad9862_regs.soft_reset = 1;
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this->send_reg(0);
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//initialize the codec register settings
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_ad9862_regs.sdio_bidir = ad9862_regs_t::SDIO_BIDIR_SDIO_SDO;
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_ad9862_regs.lsb_first = ad9862_regs_t::LSB_FIRST_MSB;
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_ad9862_regs.soft_reset = 0;
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//setup rx side of codec
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_ad9862_regs.byp_buffer_a = 1;
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_ad9862_regs.byp_buffer_b = 1;
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_ad9862_regs.buffer_a_pd = 1;
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_ad9862_regs.buffer_b_pd = 1;
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_ad9862_regs.rx_pga_a = 0;
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_ad9862_regs.rx_pga_b = 0;
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_ad9862_regs.rx_twos_comp = 1;
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_ad9862_regs.rx_hilbert = ad9862_regs_t::RX_HILBERT_DIS;
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//setup tx side of codec
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_ad9862_regs.two_data_paths = ad9862_regs_t::TWO_DATA_PATHS_BOTH;
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_ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_INTERLEAVED;
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_ad9862_regs.tx_pga_gain = 199;
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_ad9862_regs.tx_hilbert = ad9862_regs_t::TX_HILBERT_DIS;
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_ad9862_regs.interp = ad9862_regs_t::INTERP_4;
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_ad9862_regs.tx_twos_comp = 1;
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_ad9862_regs.fine_mode = ad9862_regs_t::FINE_MODE_NCO;
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_ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS;
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_ad9862_regs.dac_a_coarse_gain = 0x3;
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_ad9862_regs.dac_b_coarse_gain = 0x3;
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//setup the dll
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_ad9862_regs.input_clk_ctrl = ad9862_regs_t::INPUT_CLK_CTRL_EXTERNAL;
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_ad9862_regs.dll_mult = ad9862_regs_t::DLL_MULT_2;
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_ad9862_regs.dll_mode = ad9862_regs_t::DLL_MODE_FAST;
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//setup clockout
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_ad9862_regs.clkout2_div_factor = ad9862_regs_t::CLKOUT2_DIV_FACTOR_2;
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//write the register settings to the codec
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for (boost::uint8_t addr = 0; addr <= 25; addr++) {
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this->send_reg(addr);
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}
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//aux adc clock
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_ad9862_regs.clk_4 = ad9862_regs_t::CLK_4_1_4;
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this->send_reg(34);
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}
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usrp1_codec_ctrl_impl::~usrp1_codec_ctrl_impl(void)
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{
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//set aux dacs to zero
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this->write_aux_dac(AUX_DAC_A, 0);
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this->write_aux_dac(AUX_DAC_B, 0);
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this->write_aux_dac(AUX_DAC_C, 0);
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this->write_aux_dac(AUX_DAC_D, 0);
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//power down
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_ad9862_regs.all_rx_pd = 1;
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this->send_reg(1);
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_ad9862_regs.tx_digital_pd = 1;
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_ad9862_regs.tx_analog_pd = ad9862_regs_t::TX_ANALOG_PD_BOTH;
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this->send_reg(8);
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}
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/***********************************************************************
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* Codec Control Gain Control Methods
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**********************************************************************/
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static const int mtpgw = 255; //maximum tx pga gain word
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void usrp1_codec_ctrl_impl::set_tx_pga_gain(double gain){
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int gain_word = int(mtpgw*(gain - tx_pga_gain_range.start())/(tx_pga_gain_range.stop() - tx_pga_gain_range.start()));
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_ad9862_regs.tx_pga_gain = std::clip(gain_word, 0, mtpgw);
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this->send_reg(16);
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}
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double usrp1_codec_ctrl_impl::get_tx_pga_gain(void){
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return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.stop() - tx_pga_gain_range.start())/mtpgw) + tx_pga_gain_range.start();
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}
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static const int mrpgw = 0x14; //maximum rx pga gain word
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void usrp1_codec_ctrl_impl::set_rx_pga_gain(double gain, char which){
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int gain_word = int(mrpgw*(gain - rx_pga_gain_range.start())/(rx_pga_gain_range.stop() - rx_pga_gain_range.start()));
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gain_word = std::clip(gain_word, 0, mrpgw);
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switch(which){
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case 'A':
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_ad9862_regs.rx_pga_a = gain_word;
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this->send_reg(2);
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return;
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case 'B':
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_ad9862_regs.rx_pga_b = gain_word;
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this->send_reg(3);
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return;
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default: UHD_THROW_INVALID_CODE_PATH();
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}
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}
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double usrp1_codec_ctrl_impl::get_rx_pga_gain(char which){
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int gain_word;
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switch(which){
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case 'A': gain_word = _ad9862_regs.rx_pga_a; break;
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case 'B': gain_word = _ad9862_regs.rx_pga_b; break;
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default: UHD_THROW_INVALID_CODE_PATH();
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}
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return (gain_word*(rx_pga_gain_range.stop() - rx_pga_gain_range.start())/mrpgw) + rx_pga_gain_range.start();
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}
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/***********************************************************************
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* Codec Control AUX ADC Methods
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**********************************************************************/
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static double aux_adc_to_volts(boost::uint8_t high, boost::uint8_t low)
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{
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return double(((boost::uint16_t(high) << 2) | low)*3.3)/0x3ff;
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}
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double usrp1_codec_ctrl_impl::read_aux_adc(aux_adc_t which)
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{
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//check to see if the switch needs to be set
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bool write_switch = false;
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switch(which) {
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case AUX_ADC_A1:
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case AUX_ADC_A2:
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if (which != _last_aux_adc_a) {
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_ad9862_regs.select_a = (which == AUX_ADC_A1)?
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ad9862_regs_t::SELECT_A_AUX_ADC1: ad9862_regs_t::SELECT_A_AUX_ADC2;
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_last_aux_adc_a = which;
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write_switch = true;
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}
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break;
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case AUX_ADC_B1:
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case AUX_ADC_B2:
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if (which != _last_aux_adc_b) {
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_ad9862_regs.select_b = (which == AUX_ADC_B1)?
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ad9862_regs_t::SELECT_B_AUX_ADC1: ad9862_regs_t::SELECT_B_AUX_ADC2;
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_last_aux_adc_b = which;
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write_switch = true;
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}
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break;
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}
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//write the switch if it changed
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if(write_switch) this->send_reg(34);
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//map aux adcs to register values to read
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static const uhd::dict<aux_adc_t, boost::uint8_t> aux_dac_to_addr = boost::assign::map_list_of
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(AUX_ADC_A2, 26) (AUX_ADC_A1, 28)
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(AUX_ADC_B2, 30) (AUX_ADC_B1, 32)
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;
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//read the value
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this->recv_reg(aux_dac_to_addr[which]+0);
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this->recv_reg(aux_dac_to_addr[which]+1);
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//return the value scaled to volts
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switch(which) {
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case AUX_ADC_A1: return aux_adc_to_volts(_ad9862_regs.aux_adc_a1_9_2, _ad9862_regs.aux_adc_a1_1_0);
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case AUX_ADC_A2: return aux_adc_to_volts(_ad9862_regs.aux_adc_a2_9_2, _ad9862_regs.aux_adc_a2_1_0);
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case AUX_ADC_B1: return aux_adc_to_volts(_ad9862_regs.aux_adc_b1_9_2, _ad9862_regs.aux_adc_b1_1_0);
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case AUX_ADC_B2: return aux_adc_to_volts(_ad9862_regs.aux_adc_b2_9_2, _ad9862_regs.aux_adc_b2_1_0);
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}
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UHD_ASSERT_THROW(false);
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}
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/***********************************************************************
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* Codec Control AUX DAC Methods
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**********************************************************************/
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void usrp1_codec_ctrl_impl::write_aux_dac(aux_dac_t which, double volts)
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{
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//special case for aux dac d (aka sigma delta word)
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if (which == AUX_DAC_D) {
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boost::uint16_t dac_word = std::clip(boost::math::iround(volts*0xfff/3.3), 0, 0xfff);
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_ad9862_regs.sig_delt_11_4 = boost::uint8_t(dac_word >> 4);
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_ad9862_regs.sig_delt_3_0 = boost::uint8_t(dac_word & 0xf);
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this->send_reg(42);
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this->send_reg(43);
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return;
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}
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//calculate the dac word for aux dac a, b, c
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boost::uint8_t dac_word = std::clip(boost::math::iround(volts*0xff/3.3), 0, 0xff);
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//setup a lookup table for the aux dac params (reg ref, reg addr)
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typedef boost::tuple<boost::uint8_t*, boost::uint8_t> dac_params_t;
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uhd::dict<aux_dac_t, dac_params_t> aux_dac_to_params = boost::assign::map_list_of
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(AUX_DAC_A, dac_params_t(&_ad9862_regs.aux_dac_a, 36))
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(AUX_DAC_B, dac_params_t(&_ad9862_regs.aux_dac_b, 37))
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(AUX_DAC_C, dac_params_t(&_ad9862_regs.aux_dac_c, 38))
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;
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//set the aux dac register
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UHD_ASSERT_THROW(aux_dac_to_params.has_key(which));
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boost::uint8_t *reg_ref, reg_addr;
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boost::tie(reg_ref, reg_addr) = aux_dac_to_params[which];
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*reg_ref = dac_word;
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this->send_reg(reg_addr);
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}
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/***********************************************************************
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* Codec Control SPI Methods
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**********************************************************************/
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void usrp1_codec_ctrl_impl::send_reg(boost::uint8_t addr)
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{
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boost::uint32_t reg = _ad9862_regs.get_write_reg(addr);
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if (codec_debug) {
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std::cout.fill('0');
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std::cout << "codec control write reg: 0x";
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std::cout << std::setw(8) << std::hex << reg << std::endl;
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}
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_iface->transact_spi(_spi_slave,
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spi_config_t::EDGE_RISE, reg, 16, false);
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}
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void usrp1_codec_ctrl_impl::recv_reg(boost::uint8_t addr)
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{
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boost::uint32_t reg = _ad9862_regs.get_read_reg(addr);
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if (codec_debug) {
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std::cout.fill('0');
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std::cout << "codec control read reg: 0x";
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std::cout << std::setw(8) << std::hex << reg << std::endl;
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}
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boost::uint32_t ret = _iface->transact_spi(_spi_slave,
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spi_config_t::EDGE_RISE, reg, 16, true);
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if (codec_debug) {
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std::cout.fill('0');
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std::cout << "codec control read ret: 0x";
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std::cout << std::setw(8) << std::hex << ret << std::endl;
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}
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_ad9862_regs.set_reg(addr, boost::uint16_t(ret));
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}
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/***********************************************************************
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* DUC tuning
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**********************************************************************/
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double usrp1_codec_ctrl_impl::coarse_tune(double codec_rate, double freq)
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{
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double coarse_freq;
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double coarse_freq_1 = codec_rate / 8;
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double coarse_freq_2 = codec_rate / 4;
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double coarse_limit_1 = coarse_freq_1 / 2;
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double coarse_limit_2 = (coarse_freq_1 + coarse_freq_2) / 2;
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double max_freq = coarse_freq_2 + .09375 * codec_rate;
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if (freq < -max_freq) {
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return false;
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}
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else if (freq < -coarse_limit_2) {
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_ad9862_regs.neg_coarse_tune = ad9862_regs_t::NEG_COARSE_TUNE_NEG_SHIFT;
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_ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_FDAC_4;
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coarse_freq = -coarse_freq_2;
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}
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else if (freq < -coarse_limit_1) {
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_ad9862_regs.neg_coarse_tune = ad9862_regs_t::NEG_COARSE_TUNE_NEG_SHIFT;
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_ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_FDAC_8;
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coarse_freq = -coarse_freq_1;
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}
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else if (freq < coarse_limit_1) {
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_ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS;
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coarse_freq = 0;
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}
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else if (freq < coarse_limit_2) {
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_ad9862_regs.neg_coarse_tune = ad9862_regs_t::NEG_COARSE_TUNE_POS_SHIFT;
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_ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_FDAC_8;
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coarse_freq = coarse_freq_1;
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}
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else if (freq <= max_freq) {
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_ad9862_regs.neg_coarse_tune = ad9862_regs_t::NEG_COARSE_TUNE_POS_SHIFT;
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_ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_FDAC_4;
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coarse_freq = coarse_freq_2;
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}
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else {
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return 0;
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}
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return coarse_freq;
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}
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double usrp1_codec_ctrl_impl::fine_tune(double codec_rate, double target_freq)
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{
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static const double scale_factor = std::pow(2.0, 24);
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boost::uint32_t freq_word = boost::uint32_t(
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boost::math::round(abs((target_freq / codec_rate) * scale_factor)));
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double actual_freq = freq_word * codec_rate / scale_factor;
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if (target_freq < 0) {
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_ad9862_regs.neg_fine_tune = ad9862_regs_t::NEG_FINE_TUNE_NEG_SHIFT;
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actual_freq = -actual_freq;
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}
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else {
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_ad9862_regs.neg_fine_tune = ad9862_regs_t::NEG_FINE_TUNE_POS_SHIFT;
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}
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_ad9862_regs.fine_mode = ad9862_regs_t::FINE_MODE_NCO;
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_ad9862_regs.ftw_23_16 = (freq_word >> 16) & 0xff;
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_ad9862_regs.ftw_15_8 = (freq_word >> 8) & 0xff;
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_ad9862_regs.ftw_7_0 = (freq_word >> 0) & 0xff;
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return actual_freq;
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}
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void usrp1_codec_ctrl_impl::set_duc_freq(double freq)
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{
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double codec_rate = _clock_ctrl->get_master_clock_freq() * 2;
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double coarse_freq = coarse_tune(codec_rate, freq);
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double fine_freq = fine_tune(codec_rate / 4, freq - coarse_freq);
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if (codec_debug) {
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std::cout << "ad9862 tuning result:" << std::endl;
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std::cout << " requested: " << freq << std::endl;
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std::cout << " actual: " << coarse_freq + fine_freq << std::endl;
|
|
std::cout << " coarse freq: " << coarse_freq << std::endl;
|
|
std::cout << " fine freq: " << fine_freq << std::endl;
|
|
std::cout << " codec rate: " << codec_rate << std::endl;
|
|
}
|
|
|
|
this->send_reg(20);
|
|
this->send_reg(21);
|
|
this->send_reg(22);
|
|
this->send_reg(23);
|
|
}
|
|
|
|
void usrp1_codec_ctrl_impl::enable_tx_digital(bool enb){
|
|
_ad9862_regs.tx_digital_pd = (enb)? 0 : 1;
|
|
this->send_reg(8);
|
|
}
|
|
|
|
/***********************************************************************
|
|
* Codec Control ADC buffer bypass
|
|
* Disable this for AC-coupled daughterboards (TVRX)
|
|
* By default it is initialized TRUE.
|
|
**********************************************************************/
|
|
void usrp1_codec_ctrl_impl::bypass_adc_buffers(bool bypass) {
|
|
_ad9862_regs.byp_buffer_a = bypass;
|
|
_ad9862_regs.byp_buffer_b = bypass;
|
|
this->send_reg(2);
|
|
}
|
|
|
|
/***********************************************************************
|
|
* Codec Control Make
|
|
**********************************************************************/
|
|
usrp1_codec_ctrl::sptr usrp1_codec_ctrl::make(usrp1_iface::sptr iface,
|
|
usrp1_clock_ctrl::sptr clock,
|
|
int spi_slave)
|
|
{
|
|
return sptr(new usrp1_codec_ctrl_impl(iface, clock, spi_slave));
|
|
}
|