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uhd/tools
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Martin Braun d61baf0aea tools: Added Balints kitchen sink debug util
2014-10-09 19:56:43 +02:00
..
b200 tools: Added b2x0_side_channel.py (FX3 debug util) 2014-10-07 15:22:39 +02:00
chdr-dissector chdr-dissector: fix wireshark-1.12 detection 2014-09-23 14:34:47 -07:00
kitchen_sink tools: Added Balints kitchen sink debug util 2014-10-09 19:56:43 +02:00
uhd_dump uhd_dump: use LIBS instead of LDFLAGS 2014-09-23 13:08:45 -07:00
README.md tools: Added Balints kitchen sink debug util 2014-10-09 19:56:43 +02:00
usrp_x3xx_fpga_jtag_programmer.sh docs: Changed Xilinx ISE version from 14.4 to 14.7 2014-09-24 18:59:01 -07:00

README.md

USRP™ Tools

This folder contains tools that are useful for working with and/or debugging your USRP™ device. Tools in this directory are not part of UHD. They are either stand-alone programs or software to be used in third-party applications.

For UHD™ software tools, look in uhd/host/utils.

List of Tools

__chdr-dissector/__

This is a packet dissector for Wireshark. It allows you to view the details of a Compressed HeaDeR (CHDR) formatted-packet in Wireshark. The USRP™ B2xx and X3xx use the CHDR format.

__uhd_dump/__

This tool can be used with tcpdump to make sense of packet dumps from your network-connected USRP™ device.

__usrp_x3xx_fpga_jtag_programmer.sh__

This tool is to be used with the USRP™ X300 and X310 devices. It allows you to program the X3x0 FPGA via JTAG. Note that loading the FPGA image via JTAG does not store the FPGA in the on-device flash storage. Thus, as soon as you cycle power, the image will be lost. To permanently burn an FPGA image, please refer to uhd/host/utils/usrp_x3xx_fpga_burner.

This tool requires that Xilinx iMPACT has been installed on your system.

__kitchen_sink__

This is a debugging tool designed to test and stress connections to USRP devices.