mattprost 9c0dc99e9d tools: update FPGA functional verification tests for X3x0 mcr's & dpdk ... -Added test cases for the 184.32MHz clock rate. -Removed some extra test cases for 200MHz clock rate in order to cut down on test time. -Added DPDK test cases (copied from 10gige and 2x_10gige test cases).		2019-11-25 13:38:34 -08:00
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uhd_rf_test	tools: Make the UHD source gen a plugin for the phase alignment test	2019-01-30 10:43:32 -08:00
CMakeLists.txt	gr-usrptest: Initial creation	2017-05-26 16:01:37 -07:00
rx_settling_time.py	tools: Add tool to analyze settling time of gain of freq changes	2018-10-11 13:19:22 -07:00
uhd_phase_alignment.py	Python: Added LO source and export arguments to the phase alignment test	2019-10-10 16:54:39 -07:00
usrp_fpga_funcverif.py	tools: update FPGA functional verification tests for X3x0 mcr's & dpdk	2019-11-25 13:38:34 -08:00
usrp_phasealignment.py	gr-usrptest: Initial creation	2017-05-26 16:01:37 -07:00
usrp_selftest.py	gr-usrptest: Initial creation	2017-05-26 16:01:37 -07:00