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This adds two changes: - We assert that tile 0 / block 0 is always enabled for both ADC and DAC, even if not required by the daughterboard or RFNoC configuration to ensure it can be used as a reference in MTS. - The converter-enable check also logs more info on the tiles like this: ``` tile/block | ADC | DAC | Notes -----------+-----+-----+------ 0/0 | 1 | 1 | RX Channel 2. TX Channel 0. MTS ref tile. 0/1 | 1 | 1 | RX Channel 1. TX Channel 3. 0/2 | 0 | 1 | TX Channel 1. 0/3 | 0 | 1 | TX Channel 2. 1/0 | 1 | 1 | RX Channel 3. TX Channel 4. 1/1 | 1 | 1 | RX Channel 0. TX Channel 7. 1/2 | 0 | 1 | TX Channel 5. 1/3 | 0 | 1 | TX Channel 6. 2/0 | 1 | 0 | RX Channel 6. 2/1 | 1 | 0 | RX Channel 5. 2/2 | 0 | 0 | 2/3 | 0 | 0 | 3/0 | 1 | 0 | RX Channel 7. 3/1 | 1 | 0 | RX Channel 4. 3/2 | 0 | 0 | 3/3 | 0 | 0 | ``` |
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| .. | ||
| __init__.py.in | ||
| base.py | ||
| CMakeLists.txt | ||
| common.py | ||
| e31x.py | ||
| e31x_periphs.py | ||
| e320.py | ||
| e320_periphs.py | ||
| n3xx.py | ||
| n3xx_periphs.py | ||
| sim.py | ||
| x4xx.py | ||
| x4xx_clk_aux.py | ||
| x4xx_clock_ctrl.py | ||
| x4xx_clock_lookup.py | ||
| x4xx_clock_mgr.py | ||
| x4xx_clock_policy.py | ||
| x4xx_clock_types.py | ||
| x4xx_dio_control.py | ||
| x4xx_gps_mgr.py | ||
| x4xx_mb_cpld.py | ||
| x4xx_periphs.py | ||
| x4xx_reference_pll.py | ||
| x4xx_rfdc_ctrl.py | ||
| x4xx_rfdc_regs.py | ||
| x4xx_sample_pll.py | ||
| x4xx_update_cpld.py | ||