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7ba25a638e
So, the Python garbage collector is a bit pernicious, in that it happens behind the scenes in a way which is difficult to predict. The rfdc_ctrl class expects that its "lifetime" will be a single live/die cycle of the FPGA (i.e. that when a new FPGA is loaded, it will be destructed). However, by default the Python GC will keep the X4xxRfdcCtrl class alive for an arbitrary amount of time, meaning that it's possible that multiple (C++) rfdc_ctrl classes can be alive at a single time. When the GC reaps all of these classes, libmetal segfaults when we call metal_finish several times in a row. This change works around that issue, if not the overall GC issue, by explicitly deleting the rfdc_ctrl object.
528 lines
21 KiB
Python
528 lines
21 KiB
Python
#
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# Copyright 2019 Ettus Research, a National Instruments Company
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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X400 RFDC Control Module
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"""
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import ast
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from collections import OrderedDict
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from usrp_mpm import lib # Pulls in everything from C++-land
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from usrp_mpm.periph_manager.x4xx_rfdc_regs import RfdcRegsControl
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from usrp_mpm.rpc_server import no_rpc
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# Map the interpolation/decimation factor to fabric words.
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# Keys: is_dac (False -> ADC, True -> DAC) and factor
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FABRIC_WORDS_ARRAY = { # [is_dac][factor]
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False: {0: 16, 1: 16, 2: 8, 4: 4, 8: 2}, # ADC
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True: {0: -1, 1: -1, 2: 16, 4: 8, 8: 4} # DAC
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}
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RFDC_DEVICE_ID = 0
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class X4xxRfdcCtrl:
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"""
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Control class for the X4xx's RFDC
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"""
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# Label for RFDC UIO
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rfdc_regs_label = "rfdc-regs"
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# Describes the mapping of ADC/DAC Tiles and Blocks to DB Slot IDs
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# Follows the below structure:
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# <slot_idx>
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# 'adc': [ (<tile_number>, <block_number>), ... ]
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# 'dac': [ (<tile_number>, <block_number>), ... ]
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RFDC_DB_MAP = [
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{
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'adc': [(0, 1), (0, 0)],
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'dac': [(0, 0), (0, 1)],
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},
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{
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'adc': [(2, 1), (2, 0)],
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'dac': [(1, 0), (1, 1)],
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},
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]
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# Maps all possible master_clock_rate (data clk rate * data SPC) values to the
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# corresponding sample rate, expected FPGA decimation, whether to configure
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# the SPLL in legacy mode (which uses a different divider), and whether half-band
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# resampling is used.
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# Using an OrderedDict to use the first rates as a preference for the default
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# rate for its corresponding decimation.
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master_to_sample_clk = OrderedDict({
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# MCR: (SPLL, decimation, legacy mode, half-band resampling)
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122.88e6*4: (2.94912e9, 2, False, False), # RF (1M-8G)
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122.88e6*2: (2.94912e9, 2, False, True), # RF (1M-8G)
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122.88e6*1: (2.94912e9, 8, False, False), # RF (1M-8G)
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125e6*2: (3.00000e9, 2, False, True), # RF (1M-8G)
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125e6*4: (3.00000e9, 2, False, False), # RF (1M-8G)
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200e6: (3.00000e9, 4, True, False), # RF (Legacy Mode)
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})
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def __init__(self, get_spll_freq, log):
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self.log = log.getChild('RFDC')
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self._get_spll_freq = get_spll_freq
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self._rfdc_regs = RfdcRegsControl(self.rfdc_regs_label, self.log)
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self._rfdc_ctrl = lib.rfdc.rfdc_ctrl()
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self._rfdc_ctrl.init(RFDC_DEVICE_ID)
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# Stores the last set value of the nco freq for each channel
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# Follows the below structure:
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# <slot_id>
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# 'rx': [chan0_freq, chan1_freq]
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# 'tx': [chan0_freq, chan1_freq]
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self._rfdc_freq_cache = [
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{
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'rx': [0, 0],
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'tx': [0, 0],
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},
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{
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'rx': [0, 0],
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'tx': [0, 0],
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},
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]
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self._cal_freeze_cache = {}
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@no_rpc
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def tear_down(self):
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"""
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Removes any stored references to our owning X4xx class instance and
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destructs anything that must happen at teardown
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"""
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self._get_spll_freq = None
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del self._rfdc_ctrl
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###########################################################################
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# Public APIs (not available as MPM RPC calls)
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###########################################################################
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@no_rpc
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def set_reset(self, reset=True):
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"""
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Resets the RFDC FPGA components or takes them out of reset.
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"""
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if reset:
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# Assert RFDC AXI-S, filters and associated gearbox reset.
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self._rfdc_regs.set_reset_adc_dac_chains(reset=True)
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self._rfdc_regs.log_status()
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# Assert Radio clock PLL reset
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self._rfdc_regs.set_reset_mmcm(reset=True)
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# Resetting the MMCM will automatically disable clock buffers
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return
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# Take upstream MMCM out of reset
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self._rfdc_regs.set_reset_mmcm(reset=False)
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# Once the MMCM has locked, enable driving the clocks
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# to the rest of the design. Poll lock status for up
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# to 1 ms
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self._rfdc_regs.wait_for_mmcm_locked(timeout=0.001)
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self._rfdc_regs.set_gated_clock_enables(value=True)
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# De-assert RF signal chain reset
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self._rfdc_regs.set_reset_adc_dac_chains(reset=False)
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# Restart tiles in XRFdc
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# All ADC Tiles
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if not self._rfdc_ctrl.reset_tile(-1, False):
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self.log.warning('Error starting up ADC tiles')
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# All DAC Tiles
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if not self._rfdc_ctrl.reset_tile(-1, True):
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self.log.warning('Error starting up DAC tiles')
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# Set sample rate for all active tiles
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active_converters = set()
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for db_idx, db_info in enumerate(self.RFDC_DB_MAP):
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db_rfdc_resamp, _ = self._rfdc_regs.get_rfdc_resampling_factor(db_idx)
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for converter_type, tile_block_set in db_info.items():
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for tile, block in tile_block_set:
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is_dac = converter_type != 'adc'
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active_converter_tuple = (tile, block, db_rfdc_resamp, is_dac)
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active_converters.add(active_converter_tuple)
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for tile, block, resampling_factor, is_dac in active_converters:
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self._rfdc_ctrl.reset_mixer_settings(tile, block, is_dac)
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self._rfdc_ctrl.set_sample_rate(tile, is_dac, self._get_spll_freq())
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self._set_interpolation_decimation(tile, block, is_dac, resampling_factor)
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self._rfdc_regs.log_status()
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# Set RFDC NCO reset event source to analog SYSREF
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for tile, block, _, is_dac in active_converters:
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self._rfdc_ctrl.set_nco_event_src(tile, block, is_dac)
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@no_rpc
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def sync(self):
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"""
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Multi-tile Synchronization on both ADC and DAC
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"""
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# These numbers are determined from the procedure mentioned in
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# PG269 section "Advanced Multi-Tile Synchronization API use".
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adc_latency = 1228 # ADC delay in sample clocks
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dac_latency = 800 # DAC delay in sample clocks
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# Ideally, this would be a set to avoiding duplicate indices,
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# but we need to use a list for compatibility with the rfdc_ctrl
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# C++ interface (std::vector)
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adc_tiles_to_sync = []
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dac_tiles_to_sync = []
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rfdc_map = self.RFDC_DB_MAP
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for db_id in rfdc_map:
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for converter_type, tile_block_set in db_id.items():
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for tile, _ in tile_block_set:
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if converter_type == 'adc':
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if tile not in adc_tiles_to_sync:
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adc_tiles_to_sync.append(tile)
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else: # dac
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if tile not in dac_tiles_to_sync:
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dac_tiles_to_sync.append(tile)
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self._rfdc_ctrl.sync_tiles(adc_tiles_to_sync, False, adc_latency)
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self._rfdc_ctrl.sync_tiles(dac_tiles_to_sync, True, dac_latency)
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# We expect all sync'd tiles to have equal latencies
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# Sets don't add duplicates, so we can use that to look
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# for erroneous tiles
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adc_tile_latency_set = set()
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for tile in adc_tiles_to_sync:
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adc_tile_latency_set.add(
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self._rfdc_ctrl.get_tile_latency(tile, False))
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if len(adc_tile_latency_set) != 1:
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raise RuntimeError("ADC tiles failed to sync properly")
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dac_tile_latency_set = set()
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for tile in dac_tiles_to_sync:
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dac_tile_latency_set.add(
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self._rfdc_ctrl.get_tile_latency(tile, True))
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if len(dac_tile_latency_set) != 1:
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raise RuntimeError("DAC tiles failed to sync properly")
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@no_rpc
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def get_default_mcr(self):
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"""
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Gets the default master clock rate based on FPGA decimation
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"""
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fpga_decimation, fpga_halfband = self._rfdc_regs.get_rfdc_resampling_factor(0)
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for master_clock_rate in self.master_to_sample_clk:
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_, decimation, _, halfband = self.master_to_sample_clk[master_clock_rate]
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if decimation == fpga_decimation and fpga_halfband == halfband:
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return master_clock_rate
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raise RuntimeError('No master clock rate acceptable for current fpga '
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'with decimation of {}'.format(fpga_decimation))
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@no_rpc
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def get_dsp_bw(self):
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"""
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Return the bandwidth encoded in the RFdc registers.
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Note: This is X4xx-specific, not RFdc-specific. But this class owns the
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access to RfdcRegsControl, and the bandwidth is strongly related to the
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RFdc settings.
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"""
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return self._rfdc_regs.get_fabric_dsp_info(0)[0]
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@no_rpc
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def get_rfdc_resampling_factor(self, db_idx):
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"""
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Returns a tuple resampling_factor, halfbands.
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See RfdcRegsControl.get_rfdc_resampling_factor().
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"""
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return self._rfdc_regs.get_rfdc_resampling_factor(db_idx)
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@no_rpc
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def rfdc_restore_nco_freq(self):
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"""
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Restores previously set RFDC NCO Frequencies
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"""
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for slot_id, slot_info in enumerate(self._rfdc_freq_cache):
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for direction, channel_frequencies in slot_info.items():
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self.rfdc_set_nco_freq(direction, slot_id, 0, channel_frequencies[0])
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self.rfdc_set_nco_freq(direction, slot_id, 1, channel_frequencies[1])
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@no_rpc
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def rfdc_restore_cal_freeze(self):
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"""
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Restores the previously set calibration freeze settings
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"""
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for slot_id in [0, 1]:
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for tile_id, block_id, _ in self._find_converters(slot_id, "rx", "both"):
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if (tile_id, block_id) in self._cal_freeze_cache:
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self._rfdc_ctrl.set_cal_frozen(
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tile_id, block_id, 0
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)
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self._rfdc_ctrl.set_cal_frozen(
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tile_id,
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block_id,
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self._cal_freeze_cache[(tile_id, block_id)]
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)
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###########################################################################
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# Public APIs that get exposed as MPM RPC calls
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###########################################################################
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def rfdc_set_nco_freq(self, direction, slot_id, channel, freq):
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"""
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Sets the RFDC NCO Frequency for the specified channel
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"""
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converters = self._find_converters(slot_id, direction, channel)
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assert len(converters) == 1
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(tile_id, block_id, is_dac) = converters[0]
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if not self._rfdc_ctrl.set_if(tile_id, block_id, is_dac, freq):
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raise RuntimeError("Error setting RFDC IF Frequency")
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self._rfdc_freq_cache[slot_id][direction][channel] = freq
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return self._rfdc_ctrl.get_nco_freq(tile_id, block_id, is_dac)
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def rfdc_get_nco_freq(self, direction, slot_id, channel):
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"""
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Gets the RFDC NCO Frequency for the specified channel
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"""
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converters = self._find_converters(slot_id, direction, channel)
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assert len(converters) == 1
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(tile_id, block_id, is_dac) = converters[0]
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return self._rfdc_ctrl.get_nco_freq(tile_id, block_id, is_dac)
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### ADC cal ###############################################################
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def set_cal_frozen(self, frozen, slot_id, channel):
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"""
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Set the freeze state for the ADC cal blocks
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Usage:
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> set_cal_frozen <frozen> <slot_id> <channel>
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<frozen> should be 0 to unfreeze the calibration blocks or 1 to freeze them.
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"""
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for tile_id, block_id, _ in self._find_converters(slot_id, "rx", channel):
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self._cal_freeze_cache[(tile_id, block_id)] = frozen
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self._rfdc_ctrl.set_cal_frozen(tile_id, block_id, frozen)
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def get_cal_frozen(self, slot_id, channel):
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"""
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Get the freeze states for each ADC cal block in the channel
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Usage:
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> get_cal_frozen <slot_id> <channel>
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"""
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return [
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1 if self._rfdc_ctrl.get_cal_frozen(tile_id, block_id) else 0
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for tile_id, block_id, is_dac in self._find_converters(slot_id, "rx", channel)
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]
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def set_cal_coefs(self, channel, slot_id, cal_block, coefs):
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"""
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Manually override calibration block coefficients. You probably don't need to use this.
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"""
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self.log.trace(
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"Setting ADC cal coefficients for channel={} slot_id={} cal_block={}".format(
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channel, slot_id, cal_block))
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for tile_id, block_id, _ in self._find_converters(slot_id, "rx", channel):
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self._rfdc_ctrl.set_adc_cal_coefficients(
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tile_id, block_id, cal_block, ast.literal_eval(coefs))
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def get_cal_coefs(self, channel, slot_id, cal_block):
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"""
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Manually retrieve raw coefficients for the ADC calibration blocks.
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Usage:
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> get_cal_coefs <channel, 0-1> <slot_id, 0-1> <cal_block, 0-3>
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e.g.
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> get_cal_coefs 0 1 3
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Retrieves the coefficients for the TSCB block on channel 0 of DB 1.
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Valid values for cal_block are:
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0 - OCB1 (Unaffected by cal freeze)
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1 - OCB2 (Unaffected by cal freeze)
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2 - GCB
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3 - TSCB
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"""
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self.log.trace(
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"Getting ADC cal coefficients for channel={} slot_id={} cal_block={}".format(
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channel, slot_id, cal_block))
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result = []
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for tile_id, block_id, _ in self._find_converters(slot_id, "rx", channel):
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result.append(self._rfdc_ctrl.get_adc_cal_coefficients(tile_id, block_id, cal_block))
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return result
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### DAC mux
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def set_dac_mux_data(self, i_val, q_val):
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"""
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Sets the data which is muxed into the DACs when the DAC mux is enabled
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Usage:
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> set_dac_mux_data <I> <Q>
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e.g.
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> set_dac_mux_data 123 456
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"""
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self._rfdc_regs.set_cal_data(i_val, q_val)
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def set_dac_mux_enable(self, channel, enable):
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"""
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Sets whether the DAC mux is enabled for a given channel
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Usage:
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> set_dac_mux_enable <channel, 0-3> <enable, 1=enabled>
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e.g.
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> set_dac_mux_enable 1 0
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"""
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self._rfdc_regs.set_cal_enable(channel, bool(enable))
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### ADC thresholds
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def setup_threshold(self, slot_id, channel, threshold_idx, mode, delay, under, over):
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"""
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Configure the given ADC threshold block.
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Usage:
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> setup_threshold <slot_id> <channel> <threshold_idx> <mode> <delay> <under> <over>
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slot_id: Slot ID to configure, 0 or 1
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channel: Channel on the slot to configure, 0 or 1
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threshold_idx: Threshold block index, 0 or 1
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mode: Mode to configure, one of ["sticky_over", "sticky_under", "hysteresis"]
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delay: In hysteresis mode, number of samples before clearing flag.
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under: 0-16384, ADC codes to set the "under" threshold to
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over: 0-16384, ADC codes to set the "over" threshold to
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"""
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for tile_id, block_id, _ in self._find_converters(slot_id, "rx", channel):
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THRESHOLDS = {
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0: lib.rfdc.threshold_id_options.THRESHOLD_0,
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1: lib.rfdc.threshold_id_options.THRESHOLD_1,
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}
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MODES = {
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"sticky_over": lib.rfdc.threshold_mode_options.TRSHD_STICKY_OVER,
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"sticky_under": lib.rfdc.threshold_mode_options.TRSHD_STICKY_UNDER,
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"hysteresis": lib.rfdc.threshold_mode_options.TRSHD_HYSTERESIS,
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}
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if mode not in MODES:
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raise RuntimeError(
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f"Mode {mode} is not one of the allowable modes {list(MODES.keys())}")
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if threshold_idx not in THRESHOLDS:
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raise RuntimeError("threshold_idx must be 0 or 1")
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delay = int(delay)
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under = int(under)
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over = int(over)
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assert 0 <= under <= 16383
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assert 0 <= over <= 16383
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self._rfdc_ctrl.set_threshold_settings(
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tile_id, block_id,
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lib.rfdc.threshold_id_options.THRESHOLD_0,
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MODES[mode],
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delay,
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under,
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over)
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def get_threshold_status(self, slot_id, channel, threshold_idx):
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"""
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Read the threshold status bit for the given threshold block from the device.
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Usage:
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> get_threshold_status <slot_id> <channel> <threshold_idx>
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e.g.
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> get_threshold_status 0 1 0
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"""
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return self._rfdc_regs.get_threshold_status(slot_id, channel, threshold_idx) != 0
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###########################################################################
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# Private helpers (note: x4xx_db_iface calls into those)
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###########################################################################
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def _set_interpolation_decimation(self, tile, block, is_dac, factor):
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"""
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Set the provided interpolation/decimation factor to the
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specified ADC/DAC tile, block
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Only gets called from set_reset_rfdc().
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"""
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# Map the interpolation/decimation factor to fabric words.
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# Keys: is_dac (False -> ADC, True -> DAC) and factor
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# Disable FIFO
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self._rfdc_ctrl.set_data_fifo_state(tile, is_dac, False)
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# Define fabric rate based on given factor.
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fab_words = FABRIC_WORDS_ARRAY[is_dac].get(int(factor))
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if fab_words == -1:
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raise RuntimeError('Unsupported dec/int factor in RFDC')
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# Define dec/int constant based on integer factor
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if factor == 0:
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int_dec = lib.rfdc.interp_decim_options.INTERP_DECIM_OFF
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elif factor == 1:
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int_dec = lib.rfdc.interp_decim_options.INTERP_DECIM_1X
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elif factor == 2:
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int_dec = lib.rfdc.interp_decim_options.INTERP_DECIM_2X
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elif factor == 4:
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int_dec = lib.rfdc.interp_decim_options.INTERP_DECIM_4X
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elif factor == 8:
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int_dec = lib.rfdc.interp_decim_options.INTERP_DECIM_8X
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else:
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raise RuntimeError('Unsupported dec/int factor in RFDC')
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# Update tile, block settings...
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self.log.debug(
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"Setting %s for %s tile %d, block %d to %dx",
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('interpolation' if is_dac else 'decimation'),
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'DAC' if is_dac else 'ADC', tile, block, factor)
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if is_dac:
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# Set interpolation
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self._rfdc_ctrl.set_interpolation_factor(tile, block, int_dec)
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self.log.trace(
|
|
" interpolation: %s",
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self._rfdc_ctrl.get_interpolation_factor(tile, block).name)
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|
# Set fabric write rate
|
|
self._rfdc_ctrl.set_data_write_rate(tile, block, fab_words)
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|
self.log.trace(
|
|
" Read words: %d",
|
|
self._rfdc_ctrl.get_data_write_rate(tile, block, True))
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else: # ADC
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|
# Set decimation
|
|
self._rfdc_ctrl.set_decimation_factor(tile, block, int_dec)
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|
self.log.trace(
|
|
" Decimation: %s",
|
|
self._rfdc_ctrl.get_decimation_factor(tile, block).name)
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# Set fabric read rate
|
|
self._rfdc_ctrl.set_data_read_rate(tile, block, fab_words)
|
|
self.log.trace(
|
|
" Read words: %d",
|
|
self._rfdc_ctrl.get_data_read_rate(tile, block, False))
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|
# Clear interrupts
|
|
self._rfdc_ctrl.clear_data_fifo_interrupts(tile, block, is_dac)
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|
# Enable FIFO
|
|
self._rfdc_ctrl.set_data_fifo_state(tile, is_dac, True)
|
|
|
|
|
|
def _find_converters(self, slot, direction, channel):
|
|
"""
|
|
Returns a list of (tile_id, block_id, is_dac) tuples describing
|
|
the data converters associated with a given channel and direction.
|
|
"""
|
|
if direction not in ('rx', 'tx', 'both'):
|
|
self.log.error('Invalid direction "{}". Cannot find '
|
|
'associated data converters'.format(direction))
|
|
raise RuntimeError('Invalid direction "{}". Cannot find '
|
|
'associated data converters'.format(direction))
|
|
if str(channel) not in ('0', '1', 'both'):
|
|
self.log.error('Invalid channel "{}". Cannot find '
|
|
'associated data converters'.format(channel))
|
|
raise RuntimeError('Invalid channel "{}". Cannot find '
|
|
'associated data converters'.format(channel))
|
|
data_converters = []
|
|
rfdc_map = self.RFDC_DB_MAP[slot]
|
|
|
|
if direction in ('rx', 'both'):
|
|
if str(channel) == '0' or str(channel) == 'both':
|
|
(tile_id, block_id) = rfdc_map['adc'][0]
|
|
data_converters.append((tile_id, block_id, False))
|
|
if str(channel) == '1' or str(channel) == 'both':
|
|
(tile_id, block_id) = rfdc_map['adc'][1]
|
|
data_converters.append((tile_id, block_id, False))
|
|
if direction in ('tx', 'both'):
|
|
if str(channel) == '0' or str(channel) == 'both':
|
|
(tile_id, block_id) = rfdc_map['dac'][0]
|
|
data_converters.append((tile_id, block_id, True))
|
|
if str(channel) == '1' or str(channel) == 'both':
|
|
(tile_id, block_id) = rfdc_map['dac'][1]
|
|
data_converters.append((tile_id, block_id, True))
|
|
return data_converters
|