Javier Valenzuela c1d268917e mpm/fpga: x4xx: Major updates in preparation for future devices ... FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>		2023-05-23 09:06:17 +02:00
..
__init__.py.in
base.py	mpm: Add dboard_info to db_iface initialization	2023-04-02 22:24:31 -05:00
CMakeLists.txt	mpm: x4xx: Prepare clock management for multi-mcr	2023-05-20 11:12:51 -05:00
common.py	uhd: Add support for the USRP X410	2021-06-10 12:01:53 -05:00
e31x.py	mpm: Factor out transport API into PeriphManagerBase	2022-07-12 13:10:39 -05:00
e31x_periphs.py
e320.py	e320: Allow internal GPSDO to be powered-down via UHD session args	2022-11-16 09:51:57 -06:00
e320_periphs.py	mpm: Fix various Pylint issues	2020-07-09 00:39:11 -07:00
n3xx.py	Revert "uhd: Revert Raw UDP Host Changes"	2022-09-21 15:35:55 -07:00
n3xx_periphs.py	mpm: Look for pca953x based devices by device/name	2020-06-11 10:39:05 -05:00
sim.py	sim: Ignore mender artifact file on sim devices	2021-01-21 12:47:54 -06:00
x4xx.py	mpm/fpga: x4xx: Major updates in preparation for future devices	2023-05-23 09:06:17 +02:00
x4xx_clk_aux.py	MPM: X410: Set correct tuning word	2022-01-10 14:55:44 -06:00
x4xx_clock_ctrl.py	mpm: x4xx: Factor clock control out of X4xxClockManager	2023-05-16 18:18:56 -05:00
x4xx_clock_lookup.py	mpm/fpga: x4xx: Major updates in preparation for future devices	2023-05-23 09:06:17 +02:00
x4xx_clock_mgr.py	mpm: x4xx: Enable MMCM configuration based on policy	2023-05-22 18:27:23 -05:00
x4xx_clock_policy.py	mpm: x4xx: Enable MPM sync API for X410	2023-05-22 18:27:23 -05:00
x4xx_clock_types.py	mpm: Refactor LMK04832X4xx and LMK03328X4xx	2023-04-27 22:38:59 -05:00
x4xx_dio_control.py	mpm: x4xx: Add back SPI as source for GPIO	2022-04-29 06:08:18 -07:00
x4xx_gps_mgr.py	MPM: fix GPS lock sensor method name	2023-02-07 23:53:28 -08:00
x4xx_mb_cpld.py	mpm: x4xx: Move MB CPLD creation to factory	2023-03-09 11:10:39 -05:00
x4xx_periphs.py	mpm: x4xx: Refactor x4xx_rfdc_ctrl	2023-05-22 09:09:32 -05:00
x4xx_reference_pll.py	mpm: Refactor LMK04832X4xx and LMK03328X4xx	2023-04-27 22:38:59 -05:00
x4xx_rfdc_ctrl.py	mpm: x4xx: Enable MMCM configuration based on policy	2023-05-22 18:27:23 -05:00
x4xx_rfdc_regs.py	mpm/fpga: x4xx: Major updates in preparation for future devices	2023-05-23 09:06:17 +02:00
x4xx_sample_pll.py	MPM: Disable PRC to DB if not required	2023-05-22 08:14:23 -05:00
x4xx_update_cpld.py	cpld: Adapt CPLD updater for future X4x0 dboards	2023-04-05 13:02:18 -05:00