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https://github.com/saymrwulf/uhd.git
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ba00ff0cf5
The FSRU (aka EISCAT) was never supported in UHD 4.0. The FPGA repository never had the relevant files, and the block controller also never existed. This removes all the corresponding files from MPM, as well as some references from makefiles.
18 lines
465 B
Python
18 lines
465 B
Python
#
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# Copyright 2017 Ettus Research, a National Instruments Company
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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Dummy rx board implementation module
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"""
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from usrp_mpm.dboard_manager import DboardManagerBase
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class unknown(DboardManagerBase):
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hw_pid = 0
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special_eeprom_addrs = {}
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def __init__(self, spi_devices, eeprom_data):
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self._eeprom = eeprom_data[0] # save eeprom header
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# Do own init
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super(unknown, self).__init__()
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