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https://github.com/saymrwulf/uhd.git
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c1cc72258d
In one of the previous changes for dual-rate a wrong value for the sysref divider made it into test_two_sample_rates. This fixes this and makes the MPM tests green again.
292 lines
15 KiB
Python
292 lines
15 KiB
Python
#
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# Copyright 2023 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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import unittest
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import logging
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from base_tests import TestBase
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from usrp_mpm.periph_manager.x4xx_clock_policy import X440ClockPolicy
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from usrp_mpm.periph_manager.x4xx_clock_types import Spll1Vco
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from usrp_mpm.periph_manager.x4xx_rfdc_ctrl import X4xxRfdcCtrl
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class TestX440ClockConfig(TestBase):
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def test_4GHz(self):
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"""
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Checking values for 4 GHz converter rate
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"""
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log = logging.getLogger()
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cp = X440ClockPolicy(None, None, {}, log)
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dsp_info = {
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'num_rx_chans': 4,
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'num_tx_chans': 4,
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'bw': 1600,
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'extra_resampling': 1,
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'spc_rx': 8,
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'spc_tx': 8,
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}
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cp.set_dsp_info([dsp_info, dsp_info])
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mcr = 2e9
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ref_clock_freq = 10e6
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clk_config = cp.get_config(ref_clock_freq, (mcr, mcr))
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self.assertEqual(clk_config.mmcm_use_defaults, False)
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# We need to calculate if the values lead to what we want
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for idx, clock_rate in enumerate([mcr,mcr]):
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self.assertTrue(clk_config.rfdc_configs[idx].resampling in X4xxRfdcCtrl.RFDC_RESAMPLER)
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conv_rate = clock_rate * clk_config.rfdc_configs[idx].resampling
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self.assertEqual(clk_config.rfdc_configs[idx].conv_rate, conv_rate)
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lmk_vco_rate = clk_config.spll_config.output_divider * clk_config.spll_config.output_freq
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# Overall PLL2 N divider as combination of prescalar and n div
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pll2_n = clk_config.spll_config.pll2_prescaler * clk_config.spll_config.pll2_n_div
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self.assertEqual(lmk_vco_rate, 100e6 * pll2_n)
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mmcm_vco_rate = lmk_vco_rate / clk_config.spll_config.prc_divider * clk_config.mmcm_feedback_divider
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self.assertEqual(mmcm_vco_rate / clk_config.mmcm_output_div_map['r0_clk'], mcr / dsp_info['spc_rx'])
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self.assertEqual(mmcm_vco_rate / clk_config.mmcm_output_div_map['r1_clk'], mcr / dsp_info['spc_rx'])
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self.assertEqual(clk_config.spll_config.vcxo_freq, Spll1Vco.VCO100MHz)
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self.assertEqual(clk_config.spll_config.sysref_div, 1200)
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self.assertEqual(clk_config.spll_config.clkin0_r_div, 200)
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self.assertEqual(clk_config.spll_config.pll2_n_cal_div, clk_config.spll_config.pll2_n_div)
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def test_2_94912GHz(self):
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"""
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Checking values for default 2.94912 GHz converter rate
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"""
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log = logging.getLogger()
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cp = X440ClockPolicy(None, None, {}, log)
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dsp_info = {
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'num_rx_chans': 4,
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'num_tx_chans': 4,
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'bw': 1600,
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'extra_resampling': 1,
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'spc_rx': 8,
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'spc_tx': 8,
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}
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cp.set_dsp_info([dsp_info, dsp_info])
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mcr = 368.64e6
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ref_clock_freq = 10e6
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clk_config = cp.get_config(ref_clock_freq, [mcr, mcr])
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self.assertEqual(clk_config.mmcm_use_defaults, False)
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# This should be a rate that we can achieve with PLL bypass:
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self.assertEqual(clk_config.rfdc_configs[0].conv_rate, clk_config.spll_config.output_freq)
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# We need to calculate if the values lead to what we want
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for idx, clock_rate in enumerate([mcr,mcr]):
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self.assertTrue(clk_config.rfdc_configs[idx].resampling in X4xxRfdcCtrl.RFDC_RESAMPLER)
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conv_rate = clock_rate * clk_config.rfdc_configs[idx].resampling
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self.assertEqual(clk_config.rfdc_configs[idx].conv_rate, conv_rate)
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lmk_vco_rate = clk_config.spll_config.output_divider * clk_config.spll_config.output_freq
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# Overall PLL2 N divider as combination of prescalar and n div
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pll2_n = clk_config.spll_config.pll2_prescaler * clk_config.spll_config.pll2_n_div
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self.assertEqual(lmk_vco_rate, 122.88e6 * pll2_n)
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mmcm_vco_rate = lmk_vco_rate / clk_config.spll_config.prc_divider * clk_config.mmcm_feedback_divider
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self.assertEqual(mmcm_vco_rate / clk_config.mmcm_output_div_map['r0_clk'], mcr / dsp_info['spc_rx'])
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self.assertEqual(mmcm_vco_rate / clk_config.mmcm_output_div_map['r1_clk'], mcr / dsp_info['spc_rx'])
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self.assertEqual(clk_config.spll_config.vcxo_freq, Spll1Vco.VCO122_88MHz)
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self.assertEqual(clk_config.spll_config.sysref_div, 1152)
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self.assertEqual(clk_config.spll_config.clkin0_r_div, 250)
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self.assertEqual(clk_config.spll_config.pll2_n_cal_div, clk_config.spll_config.pll2_n_div)
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def test_253_90625M_Conv_Rate(self):
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"""
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Checking values for difficult master clock rate of 253.90625 MHz
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"""
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log = logging.getLogger()
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cp = X440ClockPolicy(None, None, {}, log)
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dsp_info = {
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'num_rx_chans': 4,
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'num_tx_chans': 4,
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'bw': 1600,
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'extra_resampling': 1,
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'spc_rx': 8,
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'spc_tx': 8,
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}
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cp.set_dsp_info([dsp_info, dsp_info])
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mcr = {253.90625e6}
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ref_clock_freq = 10e6
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mcr = cp.coerce_mcr(mcr)
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clk_config = cp.get_config(ref_clock_freq, mcr)
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self.assertEqual(clk_config.mmcm_use_defaults, False)
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# We need to calculate if the values lead to what we want
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for idx, clock_rate in enumerate(mcr):
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self.assertTrue(clk_config.rfdc_configs[idx].resampling in X4xxRfdcCtrl.RFDC_RESAMPLER)
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conv_rate = clock_rate * clk_config.rfdc_configs[idx].resampling
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self.assertEqual(clk_config.rfdc_configs[idx].conv_rate, conv_rate)
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lmk_vco_rate = clk_config.spll_config.output_divider * clk_config.spll_config.output_freq
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# Overall PLL2 N divider as combination of prescalar and n div
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pll2_n = clk_config.spll_config.pll2_prescaler * clk_config.spll_config.pll2_n_div
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self.assertEqual(lmk_vco_rate, 100e6 * pll2_n)
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mmcm_vco_rate = lmk_vco_rate / clk_config.spll_config.prc_divider * clk_config.mmcm_feedback_divider
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self.assertEqual(mmcm_vco_rate / clk_config.mmcm_output_div_map['r0_clk'], mcr[0] / dsp_info['spc_rx'])
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self.assertEqual(mmcm_vco_rate / clk_config.mmcm_output_div_map['r1_clk'], mcr[1] / dsp_info['spc_rx'])
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self.assertEqual(clk_config.spll_config.vcxo_freq, Spll1Vco.VCO100MHz)
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self.assertEqual(clk_config.spll_config.sysref_div, 6400)
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self.assertEqual(clk_config.spll_config.clkin0_r_div, 200)
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self.assertEqual(clk_config.spll_config.pll2_n_cal_div, clk_config.spll_config.pll2_n_div)
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def test_two_sample_rates(self):
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"""
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Checking values for two different master clock rates
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"""
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log = logging.getLogger()
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cp = X440ClockPolicy(None, None, {}, log)
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dsp_info = {
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'num_rx_chans': 4,
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'num_tx_chans': 4,
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'bw': 1600,
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'extra_resampling': 1,
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'spc_rx': 8,
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'spc_tx': 8,
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}
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cp.set_dsp_info([dsp_info, dsp_info])
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mcr = (250e6, 1500e6)
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ref_clock_freq = 10e6
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mcr = cp.coerce_mcr(mcr)
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clk_config = cp.get_config(ref_clock_freq, mcr)
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self.assertEqual(clk_config.mmcm_use_defaults, False)
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# We need to calculate if the values lead to what we want
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for idx, clock_rate in enumerate(mcr):
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self.assertTrue(clk_config.rfdc_configs[idx].resampling in X4xxRfdcCtrl.RFDC_RESAMPLER)
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conv_rate = clock_rate * clk_config.rfdc_configs[idx].resampling
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self.assertEqual(clk_config.rfdc_configs[idx].conv_rate, conv_rate)
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lmk_vco_rate = clk_config.spll_config.output_divider * clk_config.spll_config.output_freq
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# Overall PLL2 N divider as combination of prescalar and n div
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pll2_n = clk_config.spll_config.pll2_prescaler * clk_config.spll_config.pll2_n_div
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self.assertEqual(lmk_vco_rate, 100e6 * pll2_n)
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mmcm_vco_rate = lmk_vco_rate / clk_config.spll_config.prc_divider * clk_config.mmcm_feedback_divider
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self.assertEqual(mmcm_vco_rate / clk_config.mmcm_output_div_map['r0_clk'], mcr[0] / dsp_info['spc_rx'])
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self.assertEqual(mmcm_vco_rate / clk_config.mmcm_output_div_map['r1_clk'], mcr[1] / dsp_info['spc_rx'])
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self.assertEqual(clk_config.spll_config.vcxo_freq, Spll1Vco.VCO100MHz)
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self.assertEqual(clk_config.spll_config.sysref_div, 2400)
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self.assertEqual(clk_config.spll_config.clkin0_r_div, 200)
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self.assertEqual(clk_config.spll_config.pll2_n_cal_div, clk_config.spll_config.pll2_n_div)
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def test_two_sample_rates_inverted(self):
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"""
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Checking that configurations are only mirrored but not completely different
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if the two MCRs are swapped
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"""
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log = logging.getLogger()
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cp = X440ClockPolicy(None, None, {}, log)
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dsp_info = {
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'num_rx_chans': 4,
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'num_tx_chans': 4,
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'bw': 1600,
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'extra_resampling': 1,
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'spc_rx': 8,
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'spc_tx': 8,
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}
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cp.set_dsp_info([dsp_info, dsp_info])
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mcr0 = [250e6, 1500e6]
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mcr1 = mcr0.copy()
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mcr1.reverse()
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ref_clock_freq = 10e6
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mcr0 = cp.coerce_mcr(mcr0)
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mcr1 = cp.coerce_mcr(mcr1)
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clk_config0 = cp.get_config(ref_clock_freq, mcr0)
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clk_config1 = cp.get_config(ref_clock_freq, mcr1)
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self.assertEqual(clk_config0.mmcm_use_defaults, False)
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self.assertEqual(clk_config1.mmcm_use_defaults, False)
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# We need to calculate if the values lead to what we want
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for idx, clock_rate in enumerate(mcr0):
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self.assertTrue(clk_config0.rfdc_configs[idx].resampling in X4xxRfdcCtrl.RFDC_RESAMPLER)
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conv_rate0 = clock_rate * clk_config0.rfdc_configs[idx].resampling
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conv_rate1 = mcr1[1-idx] * clk_config1.rfdc_configs[1-idx].resampling
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self.assertEqual(conv_rate0, conv_rate1)
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lmk_vco_rate = clk_config0.spll_config.output_divider * clk_config1.spll_config.output_freq
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# Overall PLL2 N divider as combination of prescalar and n div
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pll2_n0 = clk_config0.spll_config.pll2_prescaler * clk_config0.spll_config.pll2_n_div
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pll2_n1 = clk_config1.spll_config.pll2_prescaler * clk_config1.spll_config.pll2_n_div
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self.assertEqual(pll2_n0, pll2_n1)
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mmcm_vco_rate0 = lmk_vco_rate / clk_config0.spll_config.prc_divider * clk_config0.mmcm_feedback_divider
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mmcm_vco_rate1 = lmk_vco_rate / clk_config1.spll_config.prc_divider * clk_config1.mmcm_feedback_divider
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self.assertEqual(mmcm_vco_rate0, mmcm_vco_rate1)
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self.assertEqual(clk_config0.spll_config.sysref_div, clk_config1.spll_config.sysref_div)
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self.assertEqual(clk_config0.spll_config.clkin0_r_div, clk_config1.spll_config.clkin0_r_div)
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self.assertEqual(clk_config0.mmcm_output_div_map['r0_clk'], clk_config1.mmcm_output_div_map['r1_clk'])
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self.assertEqual(clk_config0.mmcm_output_div_map['r1_clk'], clk_config1.mmcm_output_div_map['r0_clk'])
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self.assertEqual(clk_config0.spll_config.vcxo_freq, clk_config1.spll_config.vcxo_freq)
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self.assertEqual(clk_config0.rfdc_configs[0], clk_config1.rfdc_configs[1])
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self.assertEqual(clk_config0.rfdc_configs[1], clk_config1.rfdc_configs[0])
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def test_two_incompatible_sample_rates(self):
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"""
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Checking that for incompatible sample rates we fall back to MCR0
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"""
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log = logging.getLogger()
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cp = X440ClockPolicy(None, None, {}, log)
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dsp_info = {
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'num_rx_chans': 4,
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'num_tx_chans': 4,
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'bw': 1600,
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'extra_resampling': 1,
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'spc_rx': 8,
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'spc_tx': 8,
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}
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cp.set_dsp_info([dsp_info, dsp_info])
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mcr = (1000e6, 368.64e6)
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ref_clock_freq = 10e6
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mcr = cp.coerce_mcr(mcr)
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# ...but since values are incompatible, we can focus on #0
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clk_config = cp.get_config(ref_clock_freq, mcr)
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self.assertEqual(clk_config.mmcm_use_defaults, False)
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# We need to calculate if the values lead to what we want
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for idx, clock_rate in enumerate(mcr):
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self.assertTrue(clk_config.rfdc_configs[idx].resampling in X4xxRfdcCtrl.RFDC_RESAMPLER)
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conv_rate = clock_rate * clk_config.rfdc_configs[idx].resampling
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self.assertEqual(clk_config.rfdc_configs[idx].conv_rate, conv_rate)
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lmk_vco_rate = clk_config.spll_config.output_divider * clk_config.spll_config.output_freq
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# Overall PLL2 N divider as combination of prescalar and n div
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pll2_n = clk_config.spll_config.pll2_prescaler * clk_config.spll_config.pll2_n_div
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self.assertEqual(lmk_vco_rate, 100e6 * pll2_n)
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mmcm_vco_rate = lmk_vco_rate / clk_config.spll_config.prc_divider * clk_config.mmcm_feedback_divider
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self.assertEqual(mmcm_vco_rate / clk_config.mmcm_output_div_map['r0_clk'], mcr[0] / dsp_info['spc_rx'])
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self.assertEqual(mmcm_vco_rate / clk_config.mmcm_output_div_map['r1_clk'], mcr[1] / dsp_info['spc_rx'])
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self.assertEqual(clk_config.spll_config.vcxo_freq, Spll1Vco.VCO100MHz)
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self.assertEqual(clk_config.spll_config.sysref_div, 1200)
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self.assertEqual(clk_config.spll_config.clkin0_r_div, 200)
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self.assertEqual(clk_config.spll_config.pll2_n_cal_div, clk_config.spll_config.pll2_n_div)
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def test_converter_rate_arg(self):
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"""
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Checks if the converter_rate argument is used.
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"""
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log = logging.getLogger()
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cr = 2e9
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cp = X440ClockPolicy(None, None, {'converter_rate':cr}, log)
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dsp_info = {
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'num_rx_chans': 4,
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'num_tx_chans': 4,
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'bw': 1600,
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'extra_resampling': 1,
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'spc_rx': 8,
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'spc_tx': 8,
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}
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cp.set_dsp_info([dsp_info, dsp_info])
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# In theory, for MCR=500e6, the Conv_Rate should go to 4e9. By passing the conv_rate
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# argument we should be able to influence this.
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mcr = (500e6,)
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ref_clock_freq = 10e6
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mcr = cp.coerce_mcr(mcr)
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clk_config = cp.get_config(ref_clock_freq, mcr)
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self.assertEqual(clk_config.mmcm_use_defaults, False)
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# We need to calculate if the values lead to what we want
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for idx, clock_rate in enumerate(mcr):
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self.assertTrue(clk_config.rfdc_configs[idx].resampling in X4xxRfdcCtrl.RFDC_RESAMPLER)
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conv_rate = clock_rate * clk_config.rfdc_configs[idx].resampling
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self.assertEqual(conv_rate, cr)
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self.assertEqual(clk_config.rfdc_configs[idx].conv_rate, conv_rate)
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lmk_vco_rate = clk_config.spll_config.output_divider * clk_config.spll_config.output_freq
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# Overall PLL2 N divider as combination of prescalar and n div
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pll2_n = clk_config.spll_config.pll2_prescaler * clk_config.spll_config.pll2_n_div
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self.assertEqual(lmk_vco_rate, 100e6 * pll2_n)
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mmcm_vco_rate = lmk_vco_rate / clk_config.spll_config.prc_divider * clk_config.mmcm_feedback_divider
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self.assertEqual(mmcm_vco_rate / clk_config.mmcm_output_div_map['r0_clk'], mcr[0] / dsp_info['spc_rx'])
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self.assertEqual(mmcm_vco_rate / clk_config.mmcm_output_div_map['r1_clk'], mcr[1] / dsp_info['spc_rx'])
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self.assertEqual(clk_config.spll_config.vcxo_freq, Spll1Vco.VCO100MHz)
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self.assertEqual(clk_config.spll_config.sysref_div, 1200)
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self.assertEqual(clk_config.spll_config.clkin0_r_div, 200)
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self.assertEqual(clk_config.spll_config.pll2_n_cal_div, clk_config.spll_config.pll2_n_div)
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