mirror of
https://github.com/saymrwulf/uhd.git
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99c2730bc9
- Also removes all references to boost/cstdint.hpp and replaces it with stdint.h (The 'correct' replacement would be <cstdint>, but not all of our compilers support that).
430 lines
15 KiB
C++
430 lines
15 KiB
C++
//
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// Copyright 2010-2012,2014 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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#include "codec_ctrl.hpp"
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#include "ad9862_regs.hpp"
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#include <uhd/utils/log.hpp>
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#include <uhd/utils/safe_call.hpp>
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#include <uhd/types/dict.hpp>
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#include <uhd/exception.hpp>
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#include <uhd/utils/algorithm.hpp>
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#include <uhd/utils/byteswap.hpp>
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#include <stdint.h>
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#include <boost/format.hpp>
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#include <boost/tuple/tuple.hpp>
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#include <boost/math/special_functions/round.hpp>
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#include <boost/math/special_functions/sign.hpp>
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#include <boost/assign/list_of.hpp>
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#include <iomanip>
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using namespace uhd;
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const gain_range_t usrp1_codec_ctrl::tx_pga_gain_range(-20, 0, double(0.1));
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const gain_range_t usrp1_codec_ctrl::rx_pga_gain_range(0, 20, 1);
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usrp1_codec_ctrl::~usrp1_codec_ctrl(void){
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/* NOP */
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}
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/***********************************************************************
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* Codec Control Implementation
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**********************************************************************/
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class usrp1_codec_ctrl_impl : public usrp1_codec_ctrl {
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public:
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//structors
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usrp1_codec_ctrl_impl(spi_iface::sptr iface, int spi_slave);
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~usrp1_codec_ctrl_impl(void);
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//aux adc and dac control
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double read_aux_adc(aux_adc_t which);
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void write_aux_dac(aux_dac_t which, double volts);
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//duc control
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void set_duc_freq(double freq, double);
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void enable_tx_digital(bool enb);
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//pga gain control
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void set_tx_pga_gain(double);
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double get_tx_pga_gain(void);
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void set_rx_pga_gain(double, char);
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double get_rx_pga_gain(char);
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//rx adc buffer control
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void bypass_adc_buffers(bool bypass);
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private:
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spi_iface::sptr _iface;
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int _spi_slave;
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ad9862_regs_t _ad9862_regs;
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void send_reg(uint8_t addr);
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void recv_reg(uint8_t addr);
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double coarse_tune(double codec_rate, double freq);
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double fine_tune(double codec_rate, double freq);
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};
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/***********************************************************************
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* Codec Control Structors
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**********************************************************************/
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usrp1_codec_ctrl_impl::usrp1_codec_ctrl_impl(spi_iface::sptr iface, int spi_slave){
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_iface = iface;
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_spi_slave = spi_slave;
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//soft reset
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_ad9862_regs.soft_reset = 1;
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this->send_reg(0);
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//initialize the codec register settings
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_ad9862_regs.sdio_bidir = ad9862_regs_t::SDIO_BIDIR_SDIO_SDO;
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_ad9862_regs.lsb_first = ad9862_regs_t::LSB_FIRST_MSB;
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_ad9862_regs.soft_reset = 0;
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//setup rx side of codec
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_ad9862_regs.byp_buffer_a = 1;
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_ad9862_regs.byp_buffer_b = 1;
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_ad9862_regs.buffer_a_pd = 1;
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_ad9862_regs.buffer_b_pd = 1;
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_ad9862_regs.rx_pga_a = 0;
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_ad9862_regs.rx_pga_b = 0;
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_ad9862_regs.rx_twos_comp = 1;
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_ad9862_regs.rx_hilbert = ad9862_regs_t::RX_HILBERT_DIS;
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//setup tx side of codec
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_ad9862_regs.two_data_paths = ad9862_regs_t::TWO_DATA_PATHS_BOTH;
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_ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_INTERLEAVED;
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_ad9862_regs.tx_pga_gain = 199;
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_ad9862_regs.tx_hilbert = ad9862_regs_t::TX_HILBERT_DIS;
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_ad9862_regs.interp = ad9862_regs_t::INTERP_4;
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_ad9862_regs.tx_twos_comp = 1;
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_ad9862_regs.fine_mode = ad9862_regs_t::FINE_MODE_NCO;
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_ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS;
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_ad9862_regs.dac_a_coarse_gain = 0x3;
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_ad9862_regs.dac_b_coarse_gain = 0x3;
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//setup the dll
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_ad9862_regs.input_clk_ctrl = ad9862_regs_t::INPUT_CLK_CTRL_EXTERNAL;
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_ad9862_regs.dll_mult = ad9862_regs_t::DLL_MULT_2;
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_ad9862_regs.dll_mode = ad9862_regs_t::DLL_MODE_FAST;
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//setup clockout
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_ad9862_regs.clkout2_div_factor = ad9862_regs_t::CLKOUT2_DIV_FACTOR_2;
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//write the register settings to the codec
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for (uint8_t addr = 0; addr <= 25; addr++) {
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this->send_reg(addr);
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}
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//always start conversions for aux ADC
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_ad9862_regs.start_a = 1;
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_ad9862_regs.start_b = 1;
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//aux adc clock
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_ad9862_regs.clk_4 = ad9862_regs_t::CLK_4_1_4;
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this->send_reg(34);
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}
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usrp1_codec_ctrl_impl::~usrp1_codec_ctrl_impl(void){UHD_SAFE_CALL(
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//set aux dacs to zero
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this->write_aux_dac(AUX_DAC_A, 0);
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this->write_aux_dac(AUX_DAC_B, 0);
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this->write_aux_dac(AUX_DAC_C, 0);
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this->write_aux_dac(AUX_DAC_D, 0);
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//power down
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_ad9862_regs.all_rx_pd = 1;
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this->send_reg(1);
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_ad9862_regs.tx_digital_pd = 1;
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_ad9862_regs.tx_analog_pd = ad9862_regs_t::TX_ANALOG_PD_BOTH;
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this->send_reg(8);
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)}
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/***********************************************************************
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* Codec Control Gain Control Methods
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**********************************************************************/
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static const int mtpgw = 255; //maximum tx pga gain word
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void usrp1_codec_ctrl_impl::set_tx_pga_gain(double gain){
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int gain_word = int(mtpgw*(gain - tx_pga_gain_range.start())/(tx_pga_gain_range.stop() - tx_pga_gain_range.start()));
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_ad9862_regs.tx_pga_gain = uhd::clip(gain_word, 0, mtpgw);
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this->send_reg(16);
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}
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double usrp1_codec_ctrl_impl::get_tx_pga_gain(void){
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return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.stop() - tx_pga_gain_range.start())/mtpgw) + tx_pga_gain_range.start();
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}
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static const int mrpgw = 0x14; //maximum rx pga gain word
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void usrp1_codec_ctrl_impl::set_rx_pga_gain(double gain, char which){
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int gain_word = int(mrpgw*(gain - rx_pga_gain_range.start())/(rx_pga_gain_range.stop() - rx_pga_gain_range.start()));
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gain_word = uhd::clip(gain_word, 0, mrpgw);
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switch(which){
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case 'A':
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_ad9862_regs.rx_pga_a = gain_word;
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this->send_reg(2);
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return;
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case 'B':
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_ad9862_regs.rx_pga_b = gain_word;
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this->send_reg(3);
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return;
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default: UHD_THROW_INVALID_CODE_PATH();
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}
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}
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double usrp1_codec_ctrl_impl::get_rx_pga_gain(char which){
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int gain_word;
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switch(which){
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case 'A': gain_word = _ad9862_regs.rx_pga_a; break;
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case 'B': gain_word = _ad9862_regs.rx_pga_b; break;
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default: UHD_THROW_INVALID_CODE_PATH();
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}
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return (gain_word*(rx_pga_gain_range.stop() - rx_pga_gain_range.start())/mrpgw) + rx_pga_gain_range.start();
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}
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/***********************************************************************
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* Codec Control AUX ADC Methods
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**********************************************************************/
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static double aux_adc_to_volts(uint8_t high, uint8_t low)
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{
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return double(((uint16_t(high) << 2) | low)*3.3)/0x3ff;
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}
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double usrp1_codec_ctrl_impl::read_aux_adc(aux_adc_t which){
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switch(which){
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case AUX_ADC_A1:
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_ad9862_regs.select_a = ad9862_regs_t::SELECT_A_AUX_ADC1;
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this->send_reg(34); //start conversion and select mux
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this->recv_reg(28); //read the value (2 bytes, 2 reads)
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this->recv_reg(29);
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return aux_adc_to_volts(_ad9862_regs.aux_adc_a1_9_2, _ad9862_regs.aux_adc_a1_1_0);
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case AUX_ADC_A2:
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_ad9862_regs.select_a = ad9862_regs_t::SELECT_A_AUX_ADC2;
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this->send_reg(34); //start conversion and select mux
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this->recv_reg(26); //read the value (2 bytes, 2 reads)
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this->recv_reg(27);
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return aux_adc_to_volts(_ad9862_regs.aux_adc_a2_9_2, _ad9862_regs.aux_adc_a2_1_0);
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case AUX_ADC_B1:
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_ad9862_regs.select_b = ad9862_regs_t::SELECT_B_AUX_ADC1;
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this->send_reg(34); //start conversion and select mux
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this->recv_reg(32); //read the value (2 bytes, 2 reads)
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this->recv_reg(33);
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return aux_adc_to_volts(_ad9862_regs.aux_adc_b1_9_2, _ad9862_regs.aux_adc_b1_1_0);
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case AUX_ADC_B2:
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_ad9862_regs.select_b = ad9862_regs_t::SELECT_B_AUX_ADC2;
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this->send_reg(34); //start conversion and select mux
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this->recv_reg(30); //read the value (2 bytes, 2 reads)
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this->recv_reg(31);
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return aux_adc_to_volts(_ad9862_regs.aux_adc_b2_9_2, _ad9862_regs.aux_adc_b2_1_0);
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}
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UHD_THROW_INVALID_CODE_PATH();
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}
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/***********************************************************************
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* Codec Control AUX DAC Methods
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**********************************************************************/
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void usrp1_codec_ctrl_impl::write_aux_dac(aux_dac_t which, double volts)
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{
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//special case for aux dac d (aka sigma delta word)
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if (which == AUX_DAC_D) {
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uint16_t dac_word = uhd::clip(boost::math::iround(volts*0xfff/3.3), 0, 0xfff);
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_ad9862_regs.sig_delt_11_4 = uint8_t(dac_word >> 4);
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_ad9862_regs.sig_delt_3_0 = uint8_t(dac_word & 0xf);
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this->send_reg(42);
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this->send_reg(43);
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return;
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}
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//calculate the dac word for aux dac a, b, c
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uint8_t dac_word = uhd::clip(boost::math::iround(volts*0xff/3.3), 0, 0xff);
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//setup a lookup table for the aux dac params (reg ref, reg addr)
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typedef boost::tuple<uint8_t*, uint8_t> dac_params_t;
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uhd::dict<aux_dac_t, dac_params_t> aux_dac_to_params = boost::assign::map_list_of
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(AUX_DAC_A, dac_params_t(&_ad9862_regs.aux_dac_a, 36))
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(AUX_DAC_B, dac_params_t(&_ad9862_regs.aux_dac_b, 37))
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(AUX_DAC_C, dac_params_t(&_ad9862_regs.aux_dac_c, 38))
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;
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//set the aux dac register
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UHD_ASSERT_THROW(aux_dac_to_params.has_key(which));
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uint8_t *reg_ref, reg_addr;
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boost::tie(reg_ref, reg_addr) = aux_dac_to_params[which];
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*reg_ref = dac_word;
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this->send_reg(reg_addr);
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}
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/***********************************************************************
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* Codec Control SPI Methods
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**********************************************************************/
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void usrp1_codec_ctrl_impl::send_reg(uint8_t addr)
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{
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uint32_t reg = _ad9862_regs.get_write_reg(addr);
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UHD_LOGV(often)
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<< "codec control write reg: 0x"
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<< std::setw(8) << std::hex << reg << std::endl
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;
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_iface->write_spi(_spi_slave,
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spi_config_t::EDGE_RISE, reg, 16);
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}
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void usrp1_codec_ctrl_impl::recv_reg(uint8_t addr)
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{
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uint32_t reg = _ad9862_regs.get_read_reg(addr);
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UHD_LOGV(often)
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<< "codec control read reg: 0x"
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<< std::setw(8) << std::hex << reg << std::endl
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;
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uint32_t ret = _iface->read_spi(_spi_slave,
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spi_config_t::EDGE_RISE, reg, 16);
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UHD_LOGV(often)
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<< "codec control read ret: 0x"
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<< std::setw(8) << std::hex << ret << std::endl
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;
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_ad9862_regs.set_reg(addr, uint16_t(ret));
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}
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/***********************************************************************
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* DUC tuning
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**********************************************************************/
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double usrp1_codec_ctrl_impl::coarse_tune(double codec_rate, double freq)
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{
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double coarse_freq;
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double coarse_freq_1 = codec_rate / 8;
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double coarse_freq_2 = codec_rate / 4;
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double coarse_limit_1 = coarse_freq_1 / 2;
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double coarse_limit_2 = (coarse_freq_1 + coarse_freq_2) / 2;
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double max_freq = coarse_freq_2 + .09375 * codec_rate;
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if (freq < -max_freq) {
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return false;
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}
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else if (freq < -coarse_limit_2) {
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_ad9862_regs.neg_coarse_tune = ad9862_regs_t::NEG_COARSE_TUNE_NEG_SHIFT;
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_ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_FDAC_4;
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coarse_freq = -coarse_freq_2;
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}
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else if (freq < -coarse_limit_1) {
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_ad9862_regs.neg_coarse_tune = ad9862_regs_t::NEG_COARSE_TUNE_NEG_SHIFT;
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_ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_FDAC_8;
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coarse_freq = -coarse_freq_1;
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}
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else if (freq < coarse_limit_1) {
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_ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS;
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coarse_freq = 0;
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}
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else if (freq < coarse_limit_2) {
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_ad9862_regs.neg_coarse_tune = ad9862_regs_t::NEG_COARSE_TUNE_POS_SHIFT;
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_ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_FDAC_8;
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coarse_freq = coarse_freq_1;
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}
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else if (freq <= max_freq) {
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_ad9862_regs.neg_coarse_tune = ad9862_regs_t::NEG_COARSE_TUNE_POS_SHIFT;
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_ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_FDAC_4;
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coarse_freq = coarse_freq_2;
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}
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else {
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return 0;
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}
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return coarse_freq;
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}
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double usrp1_codec_ctrl_impl::fine_tune(double codec_rate, double target_freq)
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{
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static const double scale_factor = std::pow(2.0, 24);
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uint32_t freq_word = uint32_t(
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boost::math::round(std::abs((target_freq / codec_rate) * scale_factor)));
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double actual_freq = freq_word * codec_rate / scale_factor;
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if (target_freq < 0) {
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_ad9862_regs.neg_fine_tune = ad9862_regs_t::NEG_FINE_TUNE_NEG_SHIFT;
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actual_freq = -actual_freq;
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}
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else {
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_ad9862_regs.neg_fine_tune = ad9862_regs_t::NEG_FINE_TUNE_POS_SHIFT;
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}
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_ad9862_regs.fine_mode = ad9862_regs_t::FINE_MODE_NCO;
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_ad9862_regs.ftw_23_16 = (freq_word >> 16) & 0xff;
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_ad9862_regs.ftw_15_8 = (freq_word >> 8) & 0xff;
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_ad9862_regs.ftw_7_0 = (freq_word >> 0) & 0xff;
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return actual_freq;
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}
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void usrp1_codec_ctrl_impl::set_duc_freq(double freq, double rate)
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{
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double codec_rate = rate * 2;
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//correct for outside of rate (wrap around)
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freq = std::fmod(freq, rate);
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if (std::abs(freq) > rate/2.0)
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freq -= boost::math::sign(freq)*rate;
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double coarse_freq = coarse_tune(codec_rate, freq);
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double fine_freq = fine_tune(codec_rate / 4, freq - coarse_freq);
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UHD_LOG
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<< "ad9862 tuning result:" << std::endl
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<< " requested: " << freq << std::endl
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<< " actual: " << coarse_freq + fine_freq << std::endl
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<< " coarse freq: " << coarse_freq << std::endl
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<< " fine freq: " << fine_freq << std::endl
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<< " codec rate: " << codec_rate << std::endl
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;
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this->send_reg(20);
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this->send_reg(21);
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this->send_reg(22);
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this->send_reg(23);
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}
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void usrp1_codec_ctrl_impl::enable_tx_digital(bool enb){
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_ad9862_regs.tx_digital_pd = (enb)? 0 : 1;
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this->send_reg(8);
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}
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/***********************************************************************
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* Codec Control ADC buffer bypass
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* Disable this for AC-coupled daughterboards (TVRX)
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* By default it is initialized TRUE.
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|
**********************************************************************/
|
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void usrp1_codec_ctrl_impl::bypass_adc_buffers(bool bypass) {
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|
_ad9862_regs.byp_buffer_a = bypass;
|
|
_ad9862_regs.byp_buffer_b = bypass;
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|
this->send_reg(2);
|
|
}
|
|
|
|
/***********************************************************************
|
|
* Codec Control Make
|
|
**********************************************************************/
|
|
usrp1_codec_ctrl::sptr usrp1_codec_ctrl::make(spi_iface::sptr iface,
|
|
int spi_slave)
|
|
{
|
|
return sptr(new usrp1_codec_ctrl_impl(iface, spi_slave));
|
|
}
|