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121 lines
3 KiB
C
121 lines
3 KiB
C
//
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// Copyright 2010-2011 Ettus Research LLC
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//
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/*
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* Copyright 2008 Free Software Foundation, Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <clocks.h>
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#include <stdbool.h>
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#include "memory_map.h"
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#include "ad9510.h"
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#include "spi.h"
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/*!
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* \brief Lock Detect -- Return True if our PLL is locked
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*/
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bool clocks_lock_detect();
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/*!
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* \brief Enable or disable fpga clock. Disabling would wedge and require a power cycle.
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*/
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void clocks_enable_fpga_clk(bool enable, int divisor);
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void
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clocks_init(void)
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{
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// Set up basic clocking functions in AD9510
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ad9510_write_reg(0x45, 0x01);
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//enable the 100MHz clock output to the FPGA for 50MHz CPU clock
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clocks_enable_fpga_clk(true, 1);
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//! Cannot SPI wait since SPI is on DSP clock
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//! because DSP clock goes away until DCM reset.
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//! However, spi is quick, the cpu is slow, its already ready...
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//spi_wait();
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//wait for the clock to stabilize
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while(!clocks_lock_detect());
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//issue a reset to the DCM so it locks up to the new freq
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output_regs->clk_ctrl |= CLK_RESET;
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}
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bool
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clocks_lock_detect()
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{
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return (pic_regs->pending & PIC_CLKSTATUS);
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}
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int inline
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clocks_gen_div(int divisor)
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{
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int L,H;
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L = (divisor>>1)-1;
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H = divisor-L-2;
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return (L<<4)|H;
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}
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#define CLOCK_OUT_EN 0x08
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#define CLOCK_OUT_DIS_CMOS 0x01
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#define CLOCK_OUT_DIS_PECL 0x02
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#define CLOCK_DIV_DIS 0x80
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#define CLOCK_DIV_EN 0x00
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#define CLOCK_MODE_PECL 1
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#define CLOCK_MODE_LVDS 2
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#define CLOCK_MODE_CMOS 3
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//CHANGED: set to PECL for default behavior
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void
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clocks_enable_XXX_clk(bool enable, int divisor, int reg_en, int reg_div, int mode)
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{
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int enable_word, div_word, div_en_word;
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switch(mode) {
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case CLOCK_MODE_LVDS :
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enable_word = enable ? 0x02 : 0x03;
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break;
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case CLOCK_MODE_CMOS :
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enable_word = enable ? 0x08 : 0x09;
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break;
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case CLOCK_MODE_PECL :
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default:
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enable_word = enable ? 0x08 : 0x0A;
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break;
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}
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if(enable && (divisor>1)) {
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div_word = clocks_gen_div(divisor);
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div_en_word = CLOCK_DIV_EN;
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}
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else {
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div_word = 0;
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div_en_word = CLOCK_DIV_DIS;
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}
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ad9510_write_reg(reg_en,enable_word); // Output en/dis
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ad9510_write_reg(reg_div,div_word); // Set divisor
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ad9510_write_reg(reg_div+1,div_en_word); // Enable or Bypass Divider
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ad9510_write_reg(0x5A, 0x01); // Update Regs
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}
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// Clock 1
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void
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clocks_enable_fpga_clk(bool enable, int divisor)
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{
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clocks_enable_XXX_clk(enable,divisor,0x3D,0x4A,CLOCK_MODE_PECL);
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}
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