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123 lines
3.9 KiB
C
123 lines
3.9 KiB
C
/*
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* USRP - Universal Software Radio Peripheral
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*
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* Copyright (C) 2003 Free Software Foundation, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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*/
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/*
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* common code for USRP
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*/
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#include "usrp_common.h"
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void init_board (void);
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void
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init_usrp (void)
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{
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CPUCS = bmCLKSPD1; // CPU runs @ 48 MHz
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CKCON = 0; // MOVX takes 2 cycles
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// IFCLK is generated internally and runs at 48 MHz, external clk en
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IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE;
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SYNCDELAY;
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// configure IO ports (B and D are used by slave FIFO)
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IOA = bmPORT_A_INITIAL; // Port A initial state
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OEA = bmPORT_A_OUTPUTS; // Port A direction register
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IOC = bmPORT_C_INITIAL; // Port C initial state
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OEC = bmPORT_C_OUTPUTS; // Port C direction register
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IOE = bmPORT_E_INITIAL; // Port E initial state
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OEE = bmPORT_E_OUTPUTS; // Port E direction register
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//REVCTL = bmDYN_OUT | bmENH_PKT; // highly recommended by docs
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// SYNCDELAY;
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// configure end points
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EP1OUTCFG = bmVALID | bmBULK; SYNCDELAY;
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EP1INCFG = bmVALID | bmBULK | bmIN; SYNCDELAY;
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EP2CFG = bmVALID | bmBULK | bmDOUBLEBUF; SYNCDELAY; // 512 dbl bulk OUT
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EP4CFG = bmVALID | bmBULK | bmDOUBLEBUF; SYNCDELAY; // 512 dbl bulk OUT
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EP6CFG = bmVALID | bmBULK | bmDOUBLEBUF | bmIN; SYNCDELAY; // 512 dbl bulk IN
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EP8CFG = bmVALID | bmBULK | bmDOUBLEBUF | bmIN; SYNCDELAY; // 512 dbl bulk IN
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// reset FIFOs
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FIFORESET = bmNAKALL; SYNCDELAY;
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FIFORESET = 2; SYNCDELAY;
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FIFORESET = 4; SYNCDELAY;
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FIFORESET = 6; SYNCDELAY;
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FIFORESET = 8; SYNCDELAY;
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FIFORESET = 0; SYNCDELAY;
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// configure end point FIFOs
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// let core see 0 to 1 transistion of autoin/out bit
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EP2FIFOCFG = bmWORDWIDE; SYNCDELAY;
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EP2FIFOCFG = bmAUTOOUT | bmWORDWIDE; SYNCDELAY;
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EP6FIFOCFG = bmZEROLENIN | bmWORDWIDE; SYNCDELAY;
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EP6FIFOCFG = bmZEROLENIN | bmAUTOIN | bmWORDWIDE; SYNCDELAY;
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EP4FIFOCFG = bmWORDWIDE; SYNCDELAY;
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EP4FIFOCFG = bmAUTOOUT | bmWORDWIDE; SYNCDELAY;
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EP8FIFOCFG = bmZEROLENIN | bmWORDWIDE; SYNCDELAY;
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EP8FIFOCFG = bmZEROLENIN | bmAUTOIN | bmWORDWIDE; SYNCDELAY;
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EP0BCH = 0; SYNCDELAY;
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// arm EP1OUT so we can receive "out" packets (TRM pg 8-8)
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EP1OUTBC = 0; SYNCDELAY;
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// set autoin length for EP6/EP8
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EP6AUTOINLENH = (512) >> 8; SYNCDELAY; // this is the length for high speed
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EP6AUTOINLENL = (512) & 0xff; SYNCDELAY;
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EP8AUTOINLENH = (512) >> 8; SYNCDELAY;
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EP8AUTOINLENL = (512) & 0xff; SYNCDELAY;
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//set FLAGA, FLAGB, FLAGC, FLAGD to be EP2EF, EP4EF, EP6PF, EP8PF
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PINFLAGSAB = (bmEP2EF) | (bmEP4EF << 4);
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PINFLAGSCD = (bmEP6PF) | (bmEP8PF << 4);
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//ok as far as i can tell, DECIS is reversed compared to the FX2 TRM.
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//p15.34 says DECIS high implements [assert when (fill > level)], observed opposite
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EP6FIFOPFH = 0x09;
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SYNCDELAY;
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EP6FIFOPFL = 0xFD;
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SYNCDELAY;
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EP8FIFOPFH = 0x09;
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SYNCDELAY;
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EP8FIFOPFL = 0xFD;
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SYNCDELAY;
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// EP2FIFOPFH = 0x08;
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// SYNCDELAY;
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// EP2FIFOPFL = 0x00;
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// SYNCDELAY;
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//assert FIFOEMPTY one cycle sooner so we get it in time at the FPGA
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EP2FIFOCFG |= bmBIT5;
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EP4FIFOCFG |= bmBIT5;
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//set FIFOPINPOLAR to normal (active low) mode
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FIFOPINPOLAR = 0x00;
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SYNCDELAY;
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PORTACFG = 0x80;
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init_board ();
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}
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