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This adds a new option to the "AXI-Stream Data" (axis_data) FPGA interface type. The new option, "sideband_at_end", can be added to the output port of a block's YAML description to control whether the sideband information should be sampled at the end (sideband_at_end: 1) or the beginning (sideband_at_end: 0) of the AXI-Stream packet. |
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| .. | ||
| uhd | ||
| CMakeLists.txt | ||
| config.h.in | ||
| uhd.h | ||