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31cafbb3ed
This enables the inv_sinc_ab and inv_sinc_cd flags for the DAC, turning on the inverse sinc filter.
342 lines
19 KiB
Python
342 lines
19 KiB
Python
#
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# Copyright 2018 Ettus Research, a National Instruments Company
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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DAC37J82 driver for use with Rhodium
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"""
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import time
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from builtins import object
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from ..mpmlog import get_logger
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class DAC37J82Rh(object):
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"""
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This class provides an interface to configure the DAC37J82 IC through SPI.
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"""
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DAC_VENDOR_ID = 0b01
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DAC_VERSION_ID = 0b010 # Version used in Rhodium Rev. A
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def __init__(self, slot_idx, regs_iface, parent_log=None):
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self.log = parent_log.getChild("DAC37J82") if parent_log is not None \
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else get_logger("DAC37J82-{}".format(slot_idx))
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self.slot_idx = slot_idx
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self.regs = regs_iface
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assert hasattr(self.regs, 'peek16')
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assert hasattr(self.regs, 'poke16')
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def _verify_chip_id():
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chip_id = self.regs.peek16(0x7F) & 0x001F
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self.log.trace("DAC Vendor & Version ID: 0x{:X}".format(chip_id))
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if chip_id != ((self.DAC_VENDOR_ID << 3) | self.DAC_VERSION_ID):
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self.log.error("Wrong Vendor & Version 0x{:X}".format(chip_id))
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return False
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return True
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self.reset()
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if not _verify_chip_id():
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raise RuntimeError("Unable to locate DAC37J82")
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# Define variable configuration per slot.
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# The JESD lanes going to the DAC pins are swapped differently:
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# DBA: 0 -> 0 / 1 -> 1 / 2 -> 2 / 3 -> 3
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# DBB: 0 -> 0 / 1 -> 1 / 2 -> 3 / 3 -> 2
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# Therefore, depending on the DB that is being configured, we need
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# to change the JESD lanes internal routing in the DAC to compensate
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# for the board traces swapping.
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self.lanes_ids_1 = {0: 0x0044, 1: 0x0046}[self.slot_idx] # config70
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self.lanes_ids_2 = {0: 0x190A, 1: 0x110A}[self.slot_idx] # config71
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self.octetpath_sel = {0: 0x0123, 1: 0x0132}[self.slot_idx] # config95
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self.init()
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def tx_enable(self, enable=False):
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"""
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Enable/disable the analog TX output.
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"""
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enable_bit = 0b1 if enable else 0b0
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prev_val = self.regs.peek16(0x03)
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self.regs.poke16(0x03, prev_val | enable_bit)
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def pokes16(self, addr_vals):
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"""
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Apply a series of pokes.
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pokes16((0,1),(0,2)) is the same as calling poke16(0,1), poke16(0,2).
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"""
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for addr, val in addr_vals:
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self.regs.poke16(addr, val)
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def init(self):
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"""
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Basic init that disables the analog output.
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"""
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self.tx_enable(False) # Set TXENABLE low at the DAC
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self.log.trace("DAC's Analog TX output is disabled.")
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def reset(self):
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"""
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Reset the DAC state
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"""
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self.regs.poke16(0x02, 0x2002) # Deassert the reset for the SIF registers
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self.regs.poke16(0x02, 0x2003) # Assert the reset for the SIF registers
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def config(self):
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"""
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Check the clock status, and write configuration values!
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"""
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def _check_pll_lock():
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pll_ool_alarms = self.regs.peek16(0x6C)
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if (pll_ool_alarms & 0x0008) != 0x0000:
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self.log.warning("PLL reporting unlocked... Status: 0x{:x}"
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.format(pll_ool_alarms))
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return False
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return True
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self.log.trace("Reset DAC & Clear alarm bits")
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self.reset()
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self.regs.poke16(0x6C, 0x0000) # Clear alarm bits for PLLs
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self.log.trace("DAC Configuration.")
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self.pokes16((
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(0x00, 0x001B), # config0: Interpolation 1x; ALARM enabled w/ pos. logic.
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(0x01, 0x0003), # config1: Rewriting reserved default values.
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(0x02, 0x0002), # config2: Data not zero when link not established; 2's comp. arrives at input.
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(0x03, 0x9300), # config3: Coarse DAC = 10 (9+1); TXENABLE internal is kept low.
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(0x04, 0x0000), # config4: Not masking any lane errors or FIFO flags.
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(0x05, 0x0000), # config5: Not masking any SYSREF errors, PAPs, or PLL locks.
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(0x06, 0x0000), # config6: Not masking any lane short test or loss of signal.
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(0x08, 0x0000), # config8: DAC A offset correction set to zero (default).
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(0x09, 0x0000), # config9: DAC B offset correction set to zero (default).
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(0x0A, 0x0000), # config10: DAC C offset correction set to zero (default).
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(0x0B, 0x0000), # config11: DAC D offset correction set to zero (default).
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(0x0C, 0x0400), # config12: Default quadrature correction gain A (AB path).
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(0x0D, 0x0400), # config13: Default coarse mixing options; default quadrature correction gain B (AB path).
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(0x0E, 0x0400), # config14: Default quadrature correction gain A (CD path).
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(0x0F, 0x0400), # config15: No output delays to the DACs; default quadrature correction gain A (CD path).
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(0x10, 0x0000), # config16: Default QMC correction phase (AB path).
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(0x11, 0x0000), # config17: Default QMC correction phase (AD path).
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(0x12, 0x0000), # config18: Phase offset for NCO in DACAB path (default).
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(0x13, 0x0000), # config19: Phase offset for NCO in DACAB path (default).
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(0x14, 0x0000), # config20: Lower 16 bits of NCO Frequency adjust word for DACAB path (default).
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(0x15, 0x0000), # config21: Middle 16 bits of NCO Frequency adjust word for DACAB path (default).
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(0x16, 0x0000), # config22: Upper 16 bits of NCO Frequency adjust word for DACAB path (default).
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(0x17, 0x0000), # config23: Lower 16 bits of NCO Frequency adjust word for DACCD path (default).
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(0x18, 0x0000), # config24: Middle 16 bits of NCO Frequency adjust word for DACCD path (default).
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(0x19, 0x0000), # config25: Upper 16 bits of NCO Frequency adjust word for DACCD path (default).
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(0x1A, 0x0023), # config26: DAC PLL in sleep mode; DAC C & D in sleep mode.
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(0x1B, 0x0000), # config27: Testing settings (default).
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(0x1E, 0x2222), # config30: Sync source for the QMC offset and correction: SYSREF only (Based on VST2).
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(0x1F, 0x2220), # config31: Sync source for mixers and NCO accums.: SYSREF only (Based on VST2).
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(0x20, 0x0000), # config32: Sync source for the dithering, PA protection, and FIR filter blocks: none (Based on VST2).
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(0x22, 0x1B1B), # config34: JESD and DAC routing paths (default).
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(0x23, 0x01FF), # config35: SLEEP signal from pin allowed to reach all blocks, the pin is not even used.
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(0x24, 0x0000), # config36: SYSREF syncs clock dividers: use no pulses yet.
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(0x25, 0x2000), # config37: DACCLK divider to generate JESD clock: div2. (TI recommendation).
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(0x26, 0x0000), # config38: Dithering disabled default).
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(0x2D, 0x0000), # config45: Power amplifier protection settings (default).
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(0x2E, 0xFFFF), # config46: Power amplifier protection threshold (default).
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(0x2F, 0x0004), # config47: Default values.
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(0x30, 0x0000), # config48: Constant value sent to DAC when sifdac_ena is asserted (default).
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(0x31, 0x1000), # config49: DAC PLL in reset and disabled. DACCLK is 491.52 MHz since we bypass the PLL.
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(0x32, 0x0000), # config50: DAC PLL's VCO feedback and prescaler divided (not used).
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(0x33, 0x0000), # config51: DAC PLL VCO and CP settings (not used).
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(0x34, 0x0000), # config52: SYNCB electrical configuration (default @ 1.2V CMV).
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(0x3B, 0x0000), # config59: SerDes PLL's reference. Source: DACCLK / Divider: 1 (0 +1).
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(0x3C, 0x1828), # config60: SerDes PLL Control: high loop BW; high range VCO; multiply factor x5.
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(0x3D, 0x0088), # config61: Upper configuration info for SerDes receivers (TI recommendation).
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(0x3E, 0x0128), # config62: Upper configuration for SerDes receivers:AC coupling; half rate; 20-bit width.
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(0x3F, 0x0000), # config63: No SerDes lanes inversion (default).
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(0x46, self.lanes_ids_1), # config70: JESD ID for lanes 0, 1, and 2.
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(0x47, self.lanes_ids_2), # config71: JESD ID for lanes 3, 4, and 5.
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(0x48, 0x31C3), # config72: JESD ID for lanes 6, and 7; JESD204B supported version and class (default).
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(0x49, 0x0000), # config73: JESD lanes assignment to links (default 0).
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(0x4A, 0x0F3E), # config74: Lanes 0-3 enabled; test seq. disabled; disable clocks to C/D paths.
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(0x4B, 0x1700), # config75: RBD = 24 (23 + 1) (Release Buffer Delay); F = 1 (octets per frame).
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(0x4C, 0x1703), # config76: K = 24 (23 + 1) (frames in multiframe); L = 4 (3 + 1) (number of lanes).
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(0x4D, 0x0100), # config77: M = 2 (1+1) (number of converters); S = 1 (0+1) (number of samples per frame).
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(0x4E, 0x0F4F), # config78: HD = 1 (High Density mode enabled, samples split across lanes).
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(0x4F, 0x1CC1), # config79: Match /R/ char; ILA is supported at TX.
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(0x50, 0x0000), # config80: Lane config data (link0), not used by 37J82 (default).
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(0x51, 0x00FF), # config81: Erros that cause a SYNC request (link0): all selected (default).
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(0x52, 0x00FF), # config82: Errors that are counted in err_c (link0): all selected (default).
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(0x53, 0x0000), # config83: Lane config data (link1), not used by 37J82 (default).
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(0x54, 0x0000), # config84: Erros that cause a SYNC request (link1): none selected.
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(0x55, 0x0000), # config85: Errors that are counted in err_c (link1): none selected.
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(0x56, 0x0000), # config86: Lane config data (link2), not used by 37J82 (default).
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(0x57, 0x0000), # config87: Erros that cause a SYNC request (link2): none selected.
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(0x58, 0x0000), # config88: Errors that are counted in err_c (link2): none selected.
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(0x59, 0x0000), # config89: Lane config data (link3), not used by 37J82 (default).
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(0x5A, 0x0000), # config90: Erros that cause a SYNC request (link2): none selected.
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(0x5B, 0x0000), # config91: Errors that are counted in err_c (link3): none selected.
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(0x5C, 0x0000), # config92: Links 3:1 don't use SYSREF pulses; link 0 uses no pulses yet.
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(0x5E, 0x0000), # config94: Cheksum bits for ILA, not used in 37J82 (default).
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(0x5F, self.octetpath_sel), # config95: Mapping SerDes lanes (0-3) to JESD lanes.
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(0x60, 0x4567), # config96: Mapping SerDes lanes (4-7) to JESD lanes (default).
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(0x61, 0x0001), # config97: Use only link 0 to trigger the SYNCB LVDS output.
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(0x64, 0x0703), # config100: Write to lane 0 errors to clear them (based on VST2).
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(0x65, 0x0703), # config101: Write to lane 1 errors to clear them (based on VST2).
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(0x66, 0x0703), # config102: Write to lane 2 errors to clear them (based on VST2).
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(0x67, 0x0703), # config103: Write to lane 3 errors to clear them (based on VST2).
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(0x68, 0x0703), # config104: Write to lane 4 errors to clear them (based on VST2).
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(0x69, 0x0703), # config105: Write to lane 5 errors to clear them (based on VST2).
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(0x6A, 0x0703), # config106: Write to lane 6 errors to clear them (based on VST2).
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(0x6B, 0x0703), # config107: Write to lane 7 errors to clear them (based on VST2).
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(0x6C, 0x0000), # config108: Rewrite the PLLs alarm bits clearing register.
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(0x6D, 0x0000), # config109: JESD short test alarms (default).
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(0x6E, 0x0000), # config110: Delay fractional filter settings (default).
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(0x6F, 0x0000), # config111: Delay fractional filter settings (default).
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(0x70, 0x0000), # config112: Delay fractional filter settings (default).
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(0x71, 0x0000), # config113: Delay fractional filter settings (default).
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(0x72, 0x0000), # config114: Delay fractional filter settings (default).
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(0x73, 0x0000), # config115: Delay fractional filter settings (default).
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(0x74, 0x0000), # config116: Delay fractional filter settings (default).
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(0x75, 0x0000), # config117: Delay fractional filter settings (default).
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(0x76, 0x0000), # config118: Delay fractional filter settings (default).
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(0x77, 0x0000), # config119: Delay fractional filter settings (default).
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(0x78, 0x0000), # config120: Delay fractional filter settings (default).
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(0x79, 0x0000), # config121: Delay fractional filter settings (default).
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(0x7A, 0x0000), # config122: Delay fractional filter settings (default).
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(0x7B, 0x0000), # config123: Delay fractional filter settings (default).
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(0x7C, 0x0000), # config124: Delay fractional filter settings (default).
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(0x7D, 0x0000), # config125: Delay fractional filter settings (default).
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(0x02, 0x2002), # Deassert the reset for the SIF registers
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))
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self.log.trace("DAC register dump finished.")
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self.log.trace("Polling for PLL lock...")
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locked = False
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for _ in range(6):
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time.sleep(0.001)
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# Clear stickies possibly?
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self.regs.poke16(0x6C, 0x0000) # Clear alarm bits for PLLs
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if _check_pll_lock():
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locked = True
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self.log.info("DAC PLL Locked!")
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break
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if not locked:
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raise RuntimeError("DAC PLL did not lock! Check the logs for details.")
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def enable_sysref_capture(self, enabled=False):
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"""
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Enable the SYSREF capture block, and enable divider's reset.
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"""
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self.log.trace("%s DAC SYSREF capture...",
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{True: 'Enabling', False: 'Disabling'}[enabled])
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cdrvser_sysref_mode = 0b001 if enabled else 0b000
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sysref_mode_link0 = 0b001 if enabled else 0b000
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self.regs.poke16(0x24, cdrvser_sysref_mode << 4) # Enable next SYSREF to reset the clock dividers.
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self.regs.poke16(0x5C, sysref_mode_link0 << 0) # Enable next SYSREF pulse capture for link 0.
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self.log.trace("DAC SYSREF capture %s." % {True: 'enabled', False: 'disabled'}[enabled])
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def init_deframer(self):
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"""
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Initialize the DAC's framer.
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"""
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self.log.trace("Initializing framer...")
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self.pokes16((
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(0x4A, 0x0F3F), # config74: Deassert JESD204B block reset.
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(0x4A, 0x0F21), # config74: Set JESD204B to exit init state.
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))
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self.log.trace("DAC deframer initialized.")
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def check_deframer_status(self):
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"""
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This function checks the status of the framer by checking alarms.
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"""
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ALARM_ERRORS_DESCRIPTION = {
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15 : "Multiframe alignment error",
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14 : "Frame alignment error",
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13 : "Link configuration error",
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12 : "Elastic buffer overflow",
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11 : "Elastic buffer match error",
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10 : "Code synchronization error",
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9 : "8b/10b not-in-table code error",
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8 : "8b/10b disparity error",
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3 : "FIFO write_error",
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2 : "FIFO write_full",
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1 : "FIFO read_error",
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0 : "FIFO read_empty"
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}
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self.log.trace("Checking DAC's deframer status.")
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# Clear lane alarms.
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for addr in (0x64, 0x65, 0x66, 0x67):
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self.regs.poke16(addr, 0x0000)
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time.sleep(0.001)
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# Read lane's alarms
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lanes_alarms_ary = []
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lane = 0
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for addr in (0x64, 0x65, 0x66, 0x67):
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lanes_alarms_ary.insert(lane, self.regs.peek16(addr) & 0xFF0F)
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self.log.trace("Lane {} alarms rb: 0x{:X}".format(lane, lanes_alarms_ary[lane]))
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lane += 1
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enable_analog_output = True
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# Report warnings based on an error matrix (register_width * lanes).
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errors_ary = []
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for error in range(0, 16):
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errors_ary.insert(error, [])
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# Extract errors from lanes.
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for lane in range(0, len(lanes_alarms_ary)):
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if lanes_alarms_ary[lane] & (0b1 << error) > 0:
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errors_ary[error].append(lane)
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if len(errors_ary[error]) > 0:
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enable_analog_output = False
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self.log.warning(ALARM_ERRORS_DESCRIPTION[error] +
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" in lane(s): " + ' '.join(map(str, errors_ary[error])))
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self.tx_enable(enable_analog_output)
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self.log.debug("%s analog TX output.",
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{True: 'Enabling', False: 'Disabling'}[enable_analog_output])
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return enable_analog_output
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def test_mode(self, mode='PRBS-31', lane=0):
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"""
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This method enables the DAC's test mode to verify the SerDes.
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Users should monitor the ALARM pin to see the results of the test.
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If the test is failing, ALARM will be high (or toggling if marginal).
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If the test is passing, the ALARM will be low.
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"""
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MODE_VAL = {'OFF': 0x0, 'PRBS-7': 0x2, 'PRBS-23': 0x3, 'PRBS-31': 0x4}
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assert mode.upper() in MODE_VAL
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assert lane in range(0, 8)
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self.log.debug("Setting test mode for lane {} at the DAC: {}.".format(lane, mode))
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# To run the PRBS test on the DAC, users first need to setup the DAC for
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# normal use, then make the following SPI writes:
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# 1. config74, set bits 4:0 to 0x1E to disable JESD clock.
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addr = 0x4A
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rb = self.regs.peek16(addr)
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data_w = (rb & ~0x001F) | 0x001E if mode != 'OFF' else 0x0F3E
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self.log.trace("Writing register {:02X} with {:04X}".format(addr, data_w))
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self.regs.poke16(addr, data_w)
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# 2. config61, set bits 14:12 to 0x2 to enable the 7-bit PRBS test pattern; or
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# set bits 14:12 to 0x3 to enable the 23-bit PRBS test pattern; or
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# set bits 14:12 to 0x4 to enable the 31-bit PRBS test pattern.
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addr = 0x3D
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rb = self.regs.peek16(addr)
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data_w = (rb & ~0x7000) | (MODE_VAL[mode] << 12)
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self.log.trace("Writing register {:02X} with {:04X}".format(addr, data_w))
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self.regs.poke16(addr, data_w)
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# 3. config27, set bits 11:8 to 0x3 to output PRBS testfail on ALARM pin.
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# 4. config27, set bits 14:12 to the lane to be tested (0 through 7).
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addr = 0x1B
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rb = self.regs.peek16(addr)
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data_w = (rb & ~0x7F00) | (0x3 << 8) | (lane << 12) if mode != 'OFF' else 0x0000
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self.log.trace("Writing register {:02X} with {:04X}".format(addr, data_w))
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self.regs.poke16(addr, data_w)
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# 5. config62, make sure bits 12:11 are set to 0x0 to disable character alignment.
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addr = 0x3E
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rb = self.regs.peek16(addr)
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if ((rb & 0x58) >> 11) != 0x0:
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self.log.error("Char alignment is enabled when not expected.")
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