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040d4bb0df
This splits up x4xx_clk_mgr.py into PLL controls (which go into x4xx_clock_ctrl.py) and just clock management (which stays in x4xx_clk_mgr.py).
304 lines
12 KiB
Python
304 lines
12 KiB
Python
#
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# Copyright 2021-2022 Ettus Research, a National Instruments Company
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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X4x0 Motherboard Clocking Control
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This module contains the X4xxClockCtrl class, which is the worker bee for the
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X4xxClockManager class.
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The code in this module controls the RPLL and SPLL as well as some of the muxing.
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The eCPRI PLL is controlled from the ClockingAuxBrdControl class.
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"""
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from usrp_mpm import lib # Pulls in everything from C++-land
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from usrp_mpm.sys_utils import i2c_dev
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from usrp_mpm.sys_utils.gpio import Gpio
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from usrp_mpm.sys_utils.udev import dt_symbol_get_spidev
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from usrp_mpm.periph_manager.x4xx_periphs import MboardRegsControl
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from usrp_mpm.periph_manager.x4xx_sample_pll import LMK04832X4xx
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from usrp_mpm.periph_manager.x4xx_reference_pll import LMK03328X4xx
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from usrp_mpm.periph_manager.x4xx_clock_types import \
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RpllRefSel, RpllBrcSrcSel, BrcSource
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X400_RPLL_I2C_LABEL = 'rpll_i2c'
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class X4xxClockCtrl:
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"""
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X4x0 Clocking Control
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This class controls various parts of the X4xx clocking:
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- Sample PLL (LMK04832)
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- Reference PLL (LMK03328)
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- Base Reference Clock source selection (via GPIO)
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- Clocking-related motherboard registers
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- Clocking-related settings on the motherboard CPLD
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This class exposes APIs to control all of these components. The sequencing
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logic etc. is encoded in the X4xxClockManager class.
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"""
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def __init__(self, cpld_control, log):
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# Store parent objects
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self.log = log.getChild("ClkMgr")
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self._cpld_control = cpld_control
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# Preallocate other objects to satisfy linter
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self.mboard_regs_control = None # Needs to be set later from outside!
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self._sample_pll = None
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self._reference_pll = None
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self._base_ref_clk_select = None
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# Init peripherals
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self._init_clk_peripherals()
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###########################################################################
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# Initialization code
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###########################################################################
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def _init_clk_peripherals(self):
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"""
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Initialize objects for peripherals owned by this class. Most importantly,
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this includes the RPLL and SPLL control classes.
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"""
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# Create SPI and I2C interfaces to the LMK registers
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spll_spi_node = dt_symbol_get_spidev('spll')
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sample_lmk_regs_iface = lib.spi.make_spidev_regs_iface(
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spll_spi_node,
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1000000, # Speed (Hz)
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0x3, # SPI mode
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8, # Addr shift
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0, # Data shift
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1<<23, # Read flag
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0, # Write flag
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)
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# Initialize I2C connection to RPLL
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rpll_i2c_bus = i2c_dev.dt_symbol_get_i2c_bus(X400_RPLL_I2C_LABEL)
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if rpll_i2c_bus is None:
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raise RuntimeError("RPLL I2C bus could not be found")
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self.log.trace("Using RPLL I2C bus: %s", str(rpll_i2c_bus))
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reference_lmk_regs_iface = lib.i2c.make_i2cdev_regs_iface(
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rpll_i2c_bus,
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0x54, # addr
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False, # ten_bit_addr
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100, # timeout_ms
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1 # reg_addr_size
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)
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self._sample_pll = LMK04832X4xx(sample_lmk_regs_iface, self.log)
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self._reference_pll = LMK03328X4xx(reference_lmk_regs_iface, self.log)
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# Init BRC select GPIO control
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self._base_ref_clk_select = Gpio('BASE-REFERENCE-CLOCK-SELECT', Gpio.OUTPUT, 1)
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###########################################################################
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# Low-level controls
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###########################################################################
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def reset_clock(self, value, clock_to_reset):
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"""
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Helper API to reset or re-enable a clock.
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"""
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if clock_to_reset == 'cpld':
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self._cpld_control.enable_pll_ref_clk(enable=not value)
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if clock_to_reset == 'spll':
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self._sample_pll.reset(value, hard=True)
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if clock_to_reset == 'rpll':
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self._reference_pll.reset(value, hard=True)
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def config_rpll(self,
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internal_brc_source: RpllRefSel,
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ref_rate: float,
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internal_brc_rate: float,
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usr_clk_rate: float):
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"""
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Configures the LMK03328 to generate the desired MGT reference clocks
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and internal BRC rate.
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Currently, the MGT protocol selection is not supported, but a custom
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usr_clk_rate can be generated from PLL1.
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internal_brc_source - the reference source which drives the RPLL
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(primary or secondary). Primary is the clocking
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aux card, secondary is the 100 MHz oscillator.
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ref_rate - The frequency which is being provided as reference at the
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input corresponding to internal_brc_source.
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internal_brc_rate - the rate to output as the BRC
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usr_clk_rate - the custom clock rate to generate from PLL1
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"""
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assert internal_brc_source in RpllRefSel
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assert internal_brc_source == RpllRefSel.SECONDARY or \
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ref_rate is not None
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# If the desired rate matches the rate of the primary reference source,
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# directly passthrough that reference source
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if internal_brc_source == RpllRefSel.PRIMARY and \
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internal_brc_rate == ref_rate:
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brc_select = RpllBrcSrcSel.BYPASS
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else:
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brc_select = RpllBrcSrcSel.PLL
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# TODO: Questionable if we always need to call init() here
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self._reference_pll.init()
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self._reference_pll.config(
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internal_brc_source,
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ref_rate,
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internal_brc_rate,
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usr_clk_rate,
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brc_select)
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def config_spll(self, pll_settings: dict):
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"""
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Configures the SPLL for the specified master clock rate.
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"""
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# TODO: Questionable if we always need to call init() here
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self._sample_pll.init()
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self._sample_pll.config(pll_settings)
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def get_spll_freq(self):
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"""
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Returns the output frequency setting of the SPLL that is routed to the
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ADCs/DACs.
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"""
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return self._sample_pll.output_freq
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def get_prc_rate(self):
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"""
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Returns the rate of the PLL Reference Clock (PRC) which is
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routed to the daughterboards (as an LO reference and CPLD clock) and to
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the FPGA (used to generate data_clk and rfdc_clk from the MMCM).
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Note: The PRC will change if the sample clock frequency is modified.
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"""
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return self._sample_pll.prc_freq
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def select_brc_source(self, brc_src: BrcSource):
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"""
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Configures the GaAs switch (U10/U11) that controls which BRC is used.
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"""
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if brc_src == BrcSource.RPLL:
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self._base_ref_clk_select.set(1)
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elif brc_src == BrcSource.CLK_AUX:
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self._base_ref_clk_select.set(0)
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else:
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raise RuntimeError("Invalid BRC source.")
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def sync_spll_clocks(self, pps_source: str, ref_clock_freq: float):
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"""
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Synchronize base reference clock (BRC) and PLL reference clock (PRC)
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at start of PPS trigger.
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Uses the LMK 04832 pll1_r_divider_sync to synchronize BRC with PRC.
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This sync method uses a callback to actual trigger the sync. Before
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the trigger is pulled (CLOCK_CTRL_PLL_SYNC_TRIGGER) PPS source is
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configured base on current reference clock and pps_source. After sync
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trigger the method waits for 1sec for the CLOCK_CTRL_PLL_SYNC_DONE
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to go high.
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:param pps_source: select whether internal ("internal_pps") or external
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("external_pps") PPS should be used. This parameter
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is taken into account when the current clock source
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is external. If the current clock source is set to
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internal then this parameter is not taken into
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account.
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:return: success state of sync call
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:raises RuntimeError: for invalid combinations of reference clock and
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pps_source
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"""
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def select_pps():
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"""
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Select PPS source based on current clock source and pps_source.
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This returns the bits for the motherboard CLOCK_CTRL register that
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control the PPS source.
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"""
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EXT_PPS = "external_pps"
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INT_PPS = "internal_pps"
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PPS_SOURCES = (EXT_PPS, INT_PPS)
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assert pps_source in PPS_SOURCES, \
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"%s not in %s" % (pps_source, PPS_SOURCES)
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supported_configs = {
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(10E6, EXT_PPS): MboardRegsControl.CLOCK_CTRL_PPS_EXT,
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(10E6, INT_PPS): MboardRegsControl.CLOCK_CTRL_PPS_INT_10MHz,
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(25E6, INT_PPS): MboardRegsControl.CLOCK_CTRL_PPS_INT_25MHz
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}
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config = (ref_clock_freq, pps_source)
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if config not in supported_configs:
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raise RuntimeError("Unsupported combination of reference clock "
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"(%.2E) and PPS source (%s) for PPS sync." %
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config)
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return supported_configs[config]
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return self._sample_pll.pll1_r_divider_sync(
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lambda: self.mboard_regs_control.pll_sync_trigger(select_pps()))
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def configure_pps_forwarding(
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self,
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tk_idx: int,
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enable: bool,
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master_clock_rate: float,
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delay: float = 1.0):
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"""
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Configures the PPS forwarding to the sample clock domain (master
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clock rate). This function assumes sync_spll_clocks function has
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already been executed.
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:param tk_idx: Which timekeeper to configure.
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:param enable: Boolean to choose whether PPS is forwarded to the
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sample clock domain.
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:param delay: Delay in seconds from the PPS rising edge to the edge
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occurence in the application. This value has to be in
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range 0 < x <= 1. In order to forward the PPS signal
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from base reference clock to sample clock an aligned
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rising edge of the clock is required. This can be
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created by the sync_spll_clocks function. Based on the
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greatest common divisor of the two clock rates there
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are multiple occurences of an aligned edge each second.
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One of these aligned edges has to be chosen for the
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PPS forwarding by setting this parameter.
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:return: None, Exception on error
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"""
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# FIXME MULTI_RATE enable multiple MCRs / timekeepers, use tk_idx
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return self.mboard_regs_control.configure_pps_forwarding(
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enable, master_clock_rate, self.get_prc_rate(), delay)
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def get_ref_locked(self):
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"""
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Return lock status both RPLL and SPLL.
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"""
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ref_pll_status = self._reference_pll.get_status()
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sample_pll_status = self._sample_pll.get_status()
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self.log.trace(
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f"RPLL1 lock: {ref_pll_status['PLL1 lock']} "
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f"RPLL2 lock: {ref_pll_status['PLL2 lock']} "
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f"SPLL1 lock: {sample_pll_status['PLL1 lock']} "
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f"SPLL2 lock: {sample_pll_status['PLL2 lock']}")
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return all([
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ref_pll_status['PLL1 lock'],
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ref_pll_status['PLL2 lock'],
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sample_pll_status['PLL1 lock'],
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sample_pll_status['PLL2 lock'],
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])
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###########################################################################
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# Top-level BIST APIs
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#
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# These calls will be available as MPM calls. They are only needed by BIST.
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###########################################################################
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def enable_ecpri_clocks(self, enable=True, clock='both'):
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"""
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Enable or disable the export of FABRIC and GTY_RCV eCPRI
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clocks. Main use case until we support eCPRI is manufacturing
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testing.
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"""
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self.mboard_regs_control.enable_ecpri_clocks(enable, clock)
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def get_fpga_aux_ref_freq(self):
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"""
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Return the tick count of an FPGA counter which measures the width of
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the PPS signal on the FPGA_AUX_REF FPGA input using a 40 MHz clock.
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Main use case until we support eCPRI is manufacturing testing.
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A return value of 0 indicates absence of a valid PPS signal on the
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FPGA_AUX_REF line.
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"""
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return self.mboard_regs_control.get_fpga_aux_ref_freq()
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