Martin Anderseck 68d8734f9c mpm: Add LUT for def. MCR per DSP bandwidth ... This change adds a lookup table for the default master clock rate based on the DSP bandwidth of the FPGA image for X440. Since the default master clock rate currently is 368.64 MHz and we don't want to change this for backwards compatibility, we need to have a way to handle lower bandwidth FPGA images. This is what the LUT provides.		2023-10-19 13:41:25 -05:00
..
__init__.py.in
base.py	mpmd: fix timekeeper misalignment	2023-10-09 11:01:28 -07:00
CMakeLists.txt
common.py	mpm: Add support for X440/FBX	2023-06-12 10:27:29 -05:00
e31x.py	MPM: Normalize name for gps_locked sensor	2023-08-31 15:19:12 -05:00
e31x_periphs.py
e320.py	MPM: Normalize name for gps_locked sensor	2023-08-31 15:19:12 -05:00
e320_periphs.py
n3xx.py	MPM: Normalize name for gps_locked sensor	2023-08-31 15:19:12 -05:00
n3xx_periphs.py
sim.py
x4xx.py	x4xx: pass reboot mpm command to host on new clock config for x440	2023-09-06 10:09:36 -05:00
x4xx_clk_aux.py	MPM: Normalize name for gps_locked sensor	2023-08-31 15:19:12 -05:00
x4xx_clock_ctrl.py
x4xx_clock_lookup.py	mpm: x4xx: filter MCR list	2023-07-07 12:35:55 -07:00
x4xx_clock_mgr.py	x4xx: get bool for force_reinit arg	2023-09-06 10:09:36 -05:00
x4xx_clock_policy.py	mpm: Add LUT for def. MCR per DSP bandwidth	2023-10-19 13:41:25 -05:00
x4xx_clock_types.py
x4xx_dio_control.py
x4xx_gps_mgr.py	MPM: Normalize name for gps_locked sensor	2023-08-31 15:19:12 -05:00
x4xx_mb_cpld.py	mpm: Add support for X440/FBX	2023-06-12 10:27:29 -05:00
x4xx_periphs.py	mpm: Add support for X440/FBX	2023-06-12 10:27:29 -05:00
x4xx_reference_pll.py
x4xx_rfdc_ctrl.py	SelfCal: Add startup_tile() for cal_mode selection	2023-07-07 12:35:55 -07:00
x4xx_rfdc_regs.py	mpm: Add support for X440/FBX	2023-06-12 10:27:29 -05:00
x4xx_sample_pll.py	mpm: x4xx: Improve SPLL comments	2023-06-07 07:51:21 -05:00
x4xx_update_cpld.py	mpm: Add support for X440/FBX	2023-06-12 10:27:29 -05:00