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107 lines
3.6 KiB
ReStructuredText
107 lines
3.6 KiB
ReStructuredText
========================================================================
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UHD - USRP-B100 Series Device Manual
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========================================================================
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.. contents:: Table of Contents
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------------------------------------------------------------------------
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Comparative features list
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------------------------------------------------------------------------
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**Hardware Capabilities:**
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* 1 transceiver card slot
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* External PPS reference input
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* External 10 MHz reference input
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* Configurable clock rate (defaults 64 MHz)
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**FPGA Capabilities:**
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* 1 RX DDC chain in FPGA
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* 1 TX DUC chain in FPGA
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* Timed commands in FPGA
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* Timed sampling in FPGA
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* sc8 and sc16 sample modes
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* Up to 8 MHz of RF BW with 16-bit samples
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* Up to 16 MHz of RF BW with 8-bit samples
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------------------------------------------------------------------------
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Specify a Non-standard Image
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------------------------------------------------------------------------
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UHD software will automatically select the USRP B100 images from the installed images package.
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The image selection can be overridden with the **--fpga=** and **--fw=** device address parameters.
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Example device address string representations to specify non-standard images:
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::
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fpga=usrp_b100_fpga_2rx.bin
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-- OR --
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fw=usrp_b100_fw.ihx
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------------------------------------------------------------------------
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Changing the Master Clock Rate
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------------------------------------------------------------------------
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The master clock rate of the B100 feeds both the FPGA DSP and the codec chip.
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Hundreds of rates between 32 MHz and 64 MHz are available.
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A few notable rates are:
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* **64 MHz:** maximum rate of the codec chip
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* **61.44 MHz:** good for UMTS/WCDMA applications
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* **52 MHz:** good for GSM applications
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Set 61.44 MHz - uses external VCXO
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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To use the 61.44 MHz clock rate, the USRP embedded will require one jumper to be moved,
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and X4 must be populated with a 61.44 MHz oscillator.
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* **J15** is a three pin header, move the jumper to (pin1, pin2)
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* **357LB3I061M4400** is the recommended oscillator for X4
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**Note:** See instructions below to communicate the desired clock rate into UHD software.
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Set other rates - uses internal VCO
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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To use other clock rates, the jumper will need to be in the default position.
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* **J15** is a three pin header, move the jumper to (pin2, pin3)
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To communicate the desired clock rate into UHD software,
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specify the special device address argument,
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where the key is **master_clock_rate** and the value is a rate in Hz.
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Example:
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::
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uhd_usrp_probe --args="master_clock_rate=52e6"
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------------------------------------------------------------------------
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Hardware setup notes
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------------------------------------------------------------------------
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Front panel LEDs
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The LEDs on the front panel can be useful in debugging hardware and software issues.
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The LEDs reveal the following about the state of the device:
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* **LED A:** transmitting
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* **LED B:** FPGA loaded
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* **LED C:** receiving
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* **LED D:** FPGA loaded
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* **LED E:** reference lock
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* **LED F:** board power
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------------------------------------------------------------------------
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Miscellaneous
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------------------------------------------------------------------------
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Available Sensors
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following sensors are available;
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they can be queried through the API.
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* **ref_locked:** clock reference locked (internal/external)
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