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d98e0e4994
- Add class-level attributes to store constants on the chips - LMK04832X4xx.config() is changed use a SpllConfig object, which is temporarily defined in x4xx_clk_mgr.py before calling config()
342 lines
13 KiB
Python
342 lines
13 KiB
Python
#
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# Copyright 2019 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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LMK03328 driver for use with X4xx
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"""
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from time import sleep
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from usrp_mpm.chips import LMK03328
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from usrp_mpm.sys_utils.gpio import Gpio
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from usrp_mpm.periph_manager.x4xx_clock_types import RpllRefSel, RpllBrcSrcSel
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class LMK03328X4xx(LMK03328):
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"""
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X4xx-specific subclass of the Reference Clock PLL LMK03328 controls.
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"""
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def __init__(self, pll_regs_iface, log=None):
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LMK03328.__init__(self, pll_regs_iface, log)
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self._pll_status_0 = Gpio('REFERENCE-CLOCK-PLL-STATUS-0', Gpio.INPUT)
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self._pll_status_1 = Gpio('REFERENCE-CLOCK-PLL-STATUS-1', Gpio.INPUT)
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self._pll_pwrdown_n = Gpio('REFERENCE-CLOCK-PLL-PWRDOWN', Gpio.OUTPUT, 1)
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self._reference_rates = None
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@property
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def reference_rates(self):
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"""
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Gets a list of reference source rates indexed by [primary, secondary]
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"""
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return self._reference_rates
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@reference_rates.setter
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def reference_rates(self, reference_rates):
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"""
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Sets a list of reference source rates indexed by [primary, secondary]
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"""
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assert len(reference_rates) == 2, 'Invalid number of reference rates'
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self._reference_rates = reference_rates
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def init(self):
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"""
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Perform a soft reset and verify chip ID
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"""
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# Clear hard reset
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self.reset(False, hard=True)
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# Enable sync mute
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self.poke8(0x0C, 0xC8)
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# Trigger soft reset
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self.reset(True, hard=False)
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self.reset(False, hard=False)
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if not self.verify_chip_id():
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raise Exception("unable to locate LMK03328!")
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def reset(self, value=True, hard=False):
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"""
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Perform a hard reset from the GPIO pins or a soft reset from the LMK register
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"""
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if hard:
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# The powerdown pin is active low
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self._pll_pwrdown_n.set(not value)
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else:
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self.soft_reset(value)
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def get_status(self):
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"""
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Returns PLL lock and outgoing status indicators for the LMK03328
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"""
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status_indicator_0 = self._pll_status_0.get()
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status_indicator_1 = self._pll_status_1.get()
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status_indicator = (status_indicator_1 << 1) | status_indicator_0
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return {'PLL1 lock': self.check_pll_locked(1),
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'PLL2 lock': self.check_pll_locked(2),
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'status indicator': status_indicator}
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def config(self,
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ref_select,
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ref_rate=100e6,
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brc_rate=25e6,
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usr_clk_rate=156.25e6,
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brc_select=RpllBrcSrcSel.PLL):
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"""
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Configure the RPLL to generate the desired MGT Reference clock sources
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using the specified internal BRC.
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ref_select - the reference source to use (primary=1, secondary=2)
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brc_rate - specifies the desired rate of the output BRC
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usr_clk_rate - specifies the desired rate to configure PLL1
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brc_select - specifies whether the BRC out should be from the PLL ('PLL') or
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a passthrough of the primary reference signal ('bypass')
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"""
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assert ref_select in RpllRefSel
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def calculate_out7_mux(brc_select):
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"""
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Returns the OUT7 Mux select register value based on the chosen BRC source.
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Note that OUT7 is wired to the InternalRef clock which is used as the default
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reference clock source.
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"""
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return {'bypass': 0x98, 'PLL': 0x58}[brc_select.value]
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def calculate_out7_div(brc_rate):
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""" Returns the OUT7 Divider register value based on the chosen BRC rate """
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return {25e6: 0x31, 125e6: 0x09}[brc_rate]
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def calculate_pll2_input_select(ref_select):
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""" Returns the reference mux register value based on which reference should be used """
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assert ref_select.value in (1, 2)
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return {1: 0x5B, 2: 0x7F}[ref_select.value]
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def calculate_pll2_n_div(ref_rate):
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""" Returns the PLL2 N div value based on the rate of the reference source """
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return {25e6: 0x00C8, 100e6: 0x0032}[ref_rate]
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def calculate_pll1_post_div(usr_clk_rate):
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""" Returns the PLL1 post div value based the usr_clk_rate """
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assert usr_clk_rate in (156.25e6, 125e6, 312.5e6, 161.1328125e6)
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return {
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156.25e6: 0x0E,
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125e6: 0x0E,
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312.5e6: 0x0E,
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161.1328125e6: 0x1E,
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}[usr_clk_rate]
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def calculate_pll1_n_div(usr_clk_rate):
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""" Returns the PLL1 N div value based the usr_clk_rate """
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assert usr_clk_rate in (156.25e6, 125e6, 312.5e6, 161.1328125e6)
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return {
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156.25e6: 0x0339,
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125e6: 0x0339,
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312.5e6: 0x0032,
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161.1328125e6: 0x0339,
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}[usr_clk_rate]
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def calculate_pll1_m_div(usr_clk_rate):
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""" Returns the PLL1 M div value based the usr_clk_rate """
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assert usr_clk_rate in (156.25e6, 125e6, 312.5e6, 161.1328125e6)
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return {
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156.25e6: 0x0F,
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125e6: 0x0F,
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312.5e6: 0x00,
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161.1328125e6: 0x0F,
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}[usr_clk_rate]
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def calculate_pll_select(usr_clk_rate):
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""" Returns the PLL selection based on the usr_clk_rate """
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assert usr_clk_rate in (156.25e6, 125e6)
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return {156.25e6: 2, 125e6: 2}[usr_clk_rate]
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def get_register_from_pll(pll_selection, addr):
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""" Returns the value to write to a specified register given
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the desired PLL selection. """
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assert pll_selection in (1, 2)
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assert addr in (0x22, 0x29)
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return {0x22: [0x00, 0x80], 0x29: [0x10, 0x50]}[addr][pll_selection-1]
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def calculate_out_div(usr_clk_rate):
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""" Returns the output divider for a given clock rate """
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assert usr_clk_rate in (156.25e6, 125e6)
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return {156.25e6: 0x07, 125e6: 0x09}[usr_clk_rate]
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if ref_rate not in (25e6, 100e6):
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raise RuntimeError(
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'Selected reference rate {} Hz is invalid'.format(ref_rate))
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if brc_select.value not in ('bypass', 'PLL'):
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raise RuntimeError('Selected BRC source {} is invalid'.format(brc_select))
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if brc_rate not in (25e6, 125e6):
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raise RuntimeError('Selected BRC rate {} Hz is invalid'.format(brc_rate))
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if brc_select.value == 'bypass':
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# 'bypass' sends the primary reference directly to out7
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if ref_rate != brc_rate:
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self.log.error('The specified BRC rate does not match the actual '
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'rate of the primary ref in bypass mode.')
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raise RuntimeError('The specified BRC rate does not match the actual '
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'rate of the primary ref in bypass mode.')
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if usr_clk_rate not in (156.25e6, 125e6):
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raise RuntimeError(
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f'Selected RPLL clock rate {usr_clk_rate} Hz is not supported')
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self.log.trace(
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f"Configuring RPLL to ref: {ref_select.name}, brc source: {brc_select.value} "
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f"BRC rate {brc_rate/1e6} MHz, MGT clock rate: {usr_clk_rate/1e6} MHz")
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# Config
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pll2_input_mux = calculate_pll2_input_select(ref_select)
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pll2_n_div = calculate_pll2_n_div(ref_rate)
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pll1_post_div = calculate_pll1_post_div(usr_clk_rate)
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pll1_n_div = calculate_pll1_n_div(usr_clk_rate)
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pll1_m_div = calculate_pll1_m_div(usr_clk_rate)
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pll_select = calculate_pll_select(usr_clk_rate)
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out_div = calculate_out_div(usr_clk_rate)
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out7_mux = calculate_out7_mux(brc_select)
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out7_div = calculate_out7_div(brc_rate)
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self.pokes8((
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(0x0C, 0xDF),
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(0x0D, 0x00),
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(0x0E, 0x00),
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(0x0F, 0x00),
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(0x10, 0x00),
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(0x11, 0x00),
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(0x12, 0x00),
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(0x13, 0x00),
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(0x14, 0xFF),
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(0x15, 0xFF),
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(0x16, 0xFF),
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(0x17, 0x00), # Status 0/1 mute control is disabled. Both status always ON.
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(0x18, 0x00),
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(0x19, 0x55),
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(0x1A, 0x00),
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(0x1B, 0x58),
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(0x1C, 0x58),
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(0x1D, 0x8F),
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(0x1E, 0x01),
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(0x1F, 0x00),
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(0x20, 0x00),
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(0x21, 0x00),
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(0x22, get_register_from_pll(pll_select, 0x22)),
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(0x23, 0x20),
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(0x24, out_div),
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(0x25, 0xD0),
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(0x26, 0x00),
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(0x27, 0xD0),
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(0x28, 0x09),
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(0x29, get_register_from_pll(pll_select, 0x29)),
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(0x2A, out_div),
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(0x2B, out7_mux),
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(0x2C, out7_div),
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(0x2D, 0x0A), # Disable all PLL divider status outputs. Both status pins are set to normal operation.
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(0x2E, 0x00), # Disable all PLL divider status outputs.
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(0x2F, 0x00), # Disable all PLL divider status outputs.
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(0x30, 0xFF), # Hidden register. Value from TICS software.
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(0x31, 0x0A), # set both status slew rate to slow (2.1 ns)
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(0x32, pll2_input_mux),
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(0x33, 0x03),
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(0x34, 0x00),
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(0x35, pll1_m_div),
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(0x36, 0x00),
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(0x37, 0x00),
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(0x38, pll1_post_div), # PLL1 enabled, PLL1 output reset sync enable
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(0x39, 0x08),
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(0x3A, (pll1_n_div & 0x0F00) >> 8), # PLL1 N Divider [11:8]
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(0x3B, (pll1_n_div & 0x00FF) >> 0), # PLL1 N Divider [7:0]
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(0x3C, 0x00),
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(0x3D, 0x00),
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(0x3E, 0x00),
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(0x3F, 0x00),
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(0x40, 0x00),
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(0x41, 0x01),
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(0x42, 0x0C),
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(0x43, 0x08), # PLL1 loop filter R2 = 735 ohms
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(0x44, 0x00), # PLL1 loop filter C1 = 5 pF
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(0x45, 0x00), # PLL1 loop filter R3 = 18 ohms
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(0x46, 0x00), # PLL1 loop filter C3 = 0 pF
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(0x47, 0x0E),
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(0x48, 0x08),
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(0x49, (pll2_n_div & 0x0F00) >> 8), # PLL2 N Divider [11:8]
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(0x4A, (pll2_n_div & 0x00FF) >> 0), # PLL2 N Divider [7:0]
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(0x4B, 0x00),
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(0x4C, 0x00),
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(0x4D, 0x00),
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(0x4E, 0x00),
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(0x4F, 0x00),
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(0x50, 0x01),
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(0x51, 0x0C),
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(0x52, 0x08),
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(0x53, 0x00),
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(0x54, 0x00),
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(0x55, 0x00),
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(0x56, 0x08),
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(0x57, 0x00),
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(0x58, 0x00),
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(0x59, 0xDE),
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(0x5A, 0x01),
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(0x5B, 0x18),
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(0x5C, 0x01),
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(0x5D, 0x4B),
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(0x5E, 0x01),
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(0x5F, 0x86),
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(0x60, 0x01),
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(0x61, 0xBE),
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(0x62, 0x01),
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(0x63, 0xFE),
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(0x64, 0x02),
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(0x65, 0x47),
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(0x66, 0x02),
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(0x67, 0x9E),
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(0x68, 0x00),
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(0x69, 0x00),
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(0x6A, 0x05),
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(0x6B, 0x0F),
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(0x6C, 0x0F),
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(0x6D, 0x0F),
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(0x6E, 0x0F),
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(0x6F, 0x00),
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(0x70, 0x00),
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(0x71, 0x00),
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(0x72, 0x00),
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(0x73, 0x08),
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(0x74, 0x19),
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(0x75, 0x00),
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(0x76, 0x03), # PLL1 uses 2nd order loop filter recommended for integer PLL mode.
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(0x77, 0x01),
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(0x78, 0x00),
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(0x79, 0x0F),
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(0x7A, 0x0F),
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(0x7B, 0x0F),
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(0x7C, 0x0F),
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(0x7D, 0x00),
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(0x7E, 0x00),
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(0x7F, 0x00),
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(0x80, 0x00),
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(0x81, 0x08),
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(0x82, 0x19),
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(0x83, 0x00),
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(0x84, 0x03), # PLL2 uses 2nd order loop filter recommended for integer PLL mode.
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(0x85, 0x01),
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(0x86, 0x00),
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(0x87, 0x00),
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(0x88, 0x00),
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(0x89, 0x10),
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(0x8A, 0x00),
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(0x8B, 0x00),
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(0x8C, 0x00),
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(0x8D, 0x00),
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(0x8E, 0x00),
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(0x8F, 0x00),
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(0x90, 0x00),
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(0x91, 0x00),
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(0xA9, 0x40),
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(0xAC, 0x24),
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(0xAD, 0x00),
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(0x0C, 0x5F), # Initiate VCO calibration
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(0x0C, 0xDF),
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))
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# wait for VCO calibration to be done and PLL to lock
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sleep(0.5)
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# Reset all output and PLL post dividers
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self.pokes8((
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(0x0C, 0x9F),
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(0x0C, 0xDF)
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))
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# Check for Lock
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if not self.check_pll_locked(1):
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raise RuntimeError('PLL1 did not lock!')
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if not self.check_pll_locked(2):
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raise RuntimeError('PLL2 did not lock!')
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self.log.trace("PLLs are locked!")
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