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1380b91e54
- Note on drawing power from the 3.3V rail - Clarified purpose of Pins 2 and 4 (peripheral I2C bus)
167 lines
6.2 KiB
Text
167 lines
6.2 KiB
Text
/*! \page page_gpio_api GPIO API
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\tableofcontents
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\section xgpio_fpanel The Front Panel GPIO
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All Generation-3 USRP offer an auxiliary GPIO connection
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on the motherboard itself (independent of the daughterboards). These
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GPIO pins are controlled directly by the FPGA, where they are controlled
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by an ATR (Automatic Transmit / Receive). This allows them to be toggled
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simultaneously with other radio-level changes (e.g., enabling or
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disabling a TX or RX mixer).
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For information on the X410 GPIO, see \ref page_x400_gpio_api
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\subsection xgpio_fpanel_gpio X3x0 Front Panel GPIO
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The GPIO port is not meant to drive big loads. You should not try to source more than 5mA per pin.
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The +3.3V is for ESD clamping purposes only and not designed to deliver high currents.
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\subsubsection xgpio_fpanel_conn Connector
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\image html x3x0_gpio_conn.png "X3x0 GPIO Connectors"
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\subsubsection xgpio_fpanel_pins Pin Mapping
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- Pin 1: +3.3V
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- Pin 2: Data[0]
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- Pin 3: Data[1]
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- Pin 4: Data[2]
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- Pin 5: Data[3]
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- Pin 6: Data[4]
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- Pin 7: Data[5]
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- Pin 8: Data[6]
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- Pin 9: Data[7]
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- Pin 10: Data[8]
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- Pin 11: Data[9]
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- Pin 12: Data[10]
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- Pin 13: Data[11]
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- Pin 14: 0V
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- Pin 15: 0V
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\subsection egpio_internal_gpio E310/E312/E313 Internal GPIO
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\subsubsection egpio_internal_conn Connector
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\image html e3x0_gpio_conn.png "E31x GPIO Connector"
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### Pin Mapping
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- Pin 1: +3.3V
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- Pin 2: I2C SCL (3.3 V)
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- Pin 3: Data[5]
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- Pin 4: I2C SDA (3.3 V)
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- Pin 5: Data[4]
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- Pin 6: Data[0]
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- Pin 7: Data[3]
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- Pin 8: Data[1]
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- Pin 9: 0V
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- Pin 10: Data[2]
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Pin 1 is connected to the shared +3.3V power rail and can be used to draw power.
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The maximum current depends on the power used by the rest of the device, but
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300-500 mA is generally safe. It is recommended to monitor the rail voltage
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when drawing power from this pin.
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\subsection e320_gpio_conn E320 External GPIO connector
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### Front Panel GPIO Connections
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| GPIO | Mini HDMI (Type C) | HDMI (Type A) |
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|---------|----------------------|-----------------|
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| Data[0] | Data 0+ - Pin 8 | Pin 7 |
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| Data[1] | Data 0- - Pin 9 | Pin 9 |
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| Data[2] | Clock 0+ - Pin 11 | Pin 10 |
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| Data[3] | Clock 0- - Pin 12 | Pin 12 |
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| Data[4] | CEC - Pin 14 | Pin 13 |
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| Data[5] | SCL - Pin 15 | Pin 15 |
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| Data[6] | SDA - Pin 16 | Pin 16 |
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| Data[7] | Utility - Pin 17 | Pin 14 |
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\subsection xgpio_fpanel_atr Explaining ATR
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ATR works by defining the value of the GPIO pins for certain states of
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the radio. This is the "automatic" part of it. For example, you can tell
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UHD that when the radio is transmitting and receiving (full duplex),
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GPIO6 should be high, but when it is only transmitting, GPI06 should be
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low. This state machine is set up using a series of GPIO attributes,
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with paired values and a mask, which you will want to define for the
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GPIO pins you intend to use. To set up the ATR, you use uhd::usrp::multi_usrp::set_gpio_attr().
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- **CTRL**: Is this pin controlled by ATR (automatic), or by manual
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control only?
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- **DDR**: "Data Direction Register" - defines whether or not a GPIO
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is an output or an input.
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- **OUT**: Manually set the value of a pin (only to be used in non-ATR
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mode).
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- **ATR_0X**: The status of the pins when the radio is **idle**.
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- **ATR_RX**: The status of the pins when the radio is **receiving** only.
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- **ATR_TX**: The status of the pins when the radio is **transmitting** only.
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- **ATR_XX**: The status of the pins when the radio is in **full-duplex** mode.
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The counterpart to setting the ATR (the "getter"), is called
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uhd::usrp::multi_usrp::get_gpio_attr().
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It has the exact same attributes as above, and has
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one more:
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- **READBACK**: Readback the GPIOs marked as inputs.
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\subsection xgpio_fpanel_xample An Example
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The front panel X3x0 GPIO bank is enumerated in the motherboard property
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tree (`<mb_path>/gpio/FP0/\*`), the E31x internal GPIO bank as (`<mb_path>/gpio/INT0/\`)
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and so are easily accessible through the standard uhd::usrp::multi_usrp UHD interface.
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You can discover this using the uhd::usrp::multi_usrp::get_gpio_banks() function.
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This will tell you that there is a GPIO bank on your X3x0, E320, or N3x0 called
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"FP0" (for E31x this will be called "INT0").
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This is the bank we want to set up.
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Let's say we want to use GPIO6 for an external amp. We want it to be
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automatically controlled by ATR as an output, and we want it to be high
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when we are transmitting only, and low in all other cases. We are also using
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GPIO4, which we want to control manually, as an output. We can set this
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up with the following code:
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp}
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// set up our masks, defining the pin numbers
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#define AMP_GPIO_MASK (1 << 6)
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#define MAN_GPIO_MASK (1 << 4)
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#define ATR_MASKS (AMP_GPIO_MASK | MAN_GPIO_MASK)
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// set up our values for ATR control: 1 for ATR, 0 for manual
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#define ATR_CONTROL (AMP_GPIO_MASK)
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// set up the GPIO directions: 1 for output, 0 for input
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#define GPIO_DDR (AMP_GPIO_MASK | MAN_GPIO_MASK)
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// assume an existing multi_usrp object, called "usrp"
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// now, let's do the basic ATR setup
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usrp->set_gpio_attr("FP0", "CTRL", ATR_CONTROL, ATR_MASKS);
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usrp->set_gpio_attr("FP0", "DDR", GPIO_DDR, ATR_MASKS);
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// let's manually set GPIO4 high
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usrp->set_gpio_attr("FP0", "OUT", 1, MAN_GPIO_MASK);
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// finally, let's set up GPIO6 as we described above
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usrp->set_gpio_attr("FP0", "ATR_0X", 0, AMP_GPIO_MASK);
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usrp->set_gpio_attr("FP0", "ATR_RX", 0, AMP_GPIO_MASK);
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usrp->set_gpio_attr("FP0", "ATR_TX", AMP_GPIO_MASK, AMP_GPIO_MASK);
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// usually, you would want to also make this pin go high when doing
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// full-duplex, but not in this example
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usrp->set_gpio_attr("FP0", "ATR_XX", 0, AMP_GPIO_MASK);
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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After the above code is run, the ATR in the FPGA will automatically
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control GPIO6, as we have described, based on the radio state, and we
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have direct manual control over GPIO4.
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To modify the example to work with the E31x's internal GPIO bank, use the bank
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name "INT0" instead of "FP0".
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*/
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// vim:ft=doxygen:
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