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8eeb664b67
- A PHY reset is not needed for SFP Aurora. It is only really useful when the entire quad including the commong clocking block needs to be reset
412 lines
15 KiB
Python
412 lines
15 KiB
Python
#
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# Copyright 2017 Ettus Research, National Instruments Company
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#
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# SPDX-License-Identifier: GPL-3.0
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#
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"""
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Aurora SFP control
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"""
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import math
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import time
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from builtins import str
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from builtins import object
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from usrp_mpm.mpmlog import get_logger
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def mean(vals):
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" Calculate arithmetic mean of vals "
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return float(sum(vals)) / max(len(vals), 1)
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def stddev(vals, mu=None):
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" Calculate std deviation of vals "
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mu = mu or mean(vals)
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return float(sum(((x - mu)**2 for x in vals))) / max(len(vals), 1)
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class AuroraControl(object):
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"""
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Controls an Aurora core.
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"""
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# These are relative addresses
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REG_AURORA_PORT_INFO = 0x00
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REG_AURORA_MAC_CTRL_STATUS = 0x04
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REG_AURORA_PHY_CTRL_STATUS = 0x08
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REG_AURORA_OVERRUNS = 0x20
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REG_CHECKSUM_ERRORS = 0x24
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REG_BIST_CHECKER_SAMPS = 0x28
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REG_BIST_CHECKER_ERRORS = 0x2C
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MAC_STATUS_LINK_UP_MSK = 0x00000001
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MAC_STATUS_HARD_ERR_MSK = 0x00000002
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MAC_STATUS_SOFT_ERR_MSK = 0x00000004
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MAC_STATUS_BIST_LOCKED_MSK = 0x00000008
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MAC_STATUS_BIST_LATENCY_MSK = 0x000FFFF0
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MAC_STATUS_BIST_LATENCY_OFFSET = 4
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RATE_RES_BITS = 6
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DEFAULT_BUS_CLK_RATE = 200e6
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def __init__(self, peeker_poker32, base_addr=None, bus_clk_rate=None):
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assert hasattr(peeker_poker32, 'peek32') \
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and callable(peeker_poker32.peek32)
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assert hasattr(peeker_poker32, 'poke32') \
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and callable(peeker_poker32.poke32)
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self.log = get_logger("AuroraCore")
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self._regs = peeker_poker32
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base_addr = base_addr or 0
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self.log.debug("Base address in register space is: 0x{:04X}".format(
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base_addr
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))
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self.poke32 = lambda addr, data: self._regs.poke32(
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addr + base_addr, data
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)
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self.peek32 = lambda addr: self._regs.peek32(addr + base_addr)
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self.mac_ctrl = 0x000
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self.set_mac_ctrl(self.mac_ctrl)
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time.sleep(.5)
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self.bus_clk_rate = bus_clk_rate
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if self.bus_clk_rate is None:
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self.bus_clk_rate = self.DEFAULT_BUS_CLK_RATE
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self.log.warning("Unspecified bus clock rate. Assuming default "
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"rate of {} MHz.".format(self.bus_clk_rate/1e6))
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else:
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self.log.debug("Bus clock rate: {} MHz.".format(
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self.bus_clk_rate/1e6
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))
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self.bist_max_time_limit = math.floor(2**48/self.bus_clk_rate)-1
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self.log.debug("BIST max time limit: {} s".format(
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self.bist_max_time_limit
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))
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self.log.debug("Status of PHY link: 0x{:08X}".format(
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self.read_phy_ctrl_status()
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))
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if not self.is_phy_link_up():
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raise RuntimeError("PHY link not up. Check connectors.")
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def read_mac_ctrl_status(self):
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" Return MAC ctrl status word from core "
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return self.peek32(self.REG_AURORA_MAC_CTRL_STATUS)
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def read_phy_ctrl_status(self):
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" Return PHY ctrl status word from core "
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return self.peek32(self.REG_AURORA_PHY_CTRL_STATUS)
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def read_overruns(self):
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" Return overrun count from core "
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return self.peek32(self.REG_AURORA_OVERRUNS)
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def read_checksum_errors(self):
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" Return checksum error count from core "
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return self.peek32(self.REG_CHECKSUM_ERRORS)
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def read_bist_checker_samps(self):
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" Return number of samps processed from core "
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return self.peek32(self.REG_BIST_CHECKER_SAMPS)
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def read_bist_checker_errors(self):
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" Return number of errors from core "
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return self.peek32(self.REG_BIST_CHECKER_ERRORS)
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def set_mac_ctrl(self, mac_ctrl_word):
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" Write to the MAC ctrl register "
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self.log.debug("Setting MAC ctrl word to: 0x{:08X}".format(mac_ctrl_word))
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self.poke32(self.REG_AURORA_MAC_CTRL_STATUS, mac_ctrl_word)
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def set_bist_checker_and_gen(self, enable):
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" Enable or disable Aurora BIST: Checker + Generator "
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if enable:
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self.log.info("Enable Aurora BIST Checker and Gen")
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self.mac_ctrl = self.mac_ctrl | 0b11
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else:
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self.log.info("Disable Aurora BIST Checker and Gen")
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self.mac_ctrl = self.mac_ctrl & 0xFFFFFFFC
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self.set_mac_ctrl(self.mac_ctrl)
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def set_bist_checker(self, enable):
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" Enable or disable Aurora BIST: Checker only "
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if enable:
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self.log.info("Enable Aurora BIST Checker")
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self.mac_ctrl = self.mac_ctrl | 0b01
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else:
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self.log.info("Disable Aurora BIST Checker")
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self.mac_ctrl = self.mac_ctrl & 0xFFFFFFFE
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self.set_mac_ctrl(self.mac_ctrl)
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def set_bist_gen(self, enable):
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" Enable or disable Aurora BIST: Generator only "
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if enable:
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self.log.info("Enable Aurora BIST Gen")
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self.mac_ctrl = self.mac_ctrl | 0b10
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else:
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self.log.info("Disable Aurora BIST Gen")
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self.mac_ctrl = self.mac_ctrl & 0xFFFFFFFD
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self.set_mac_ctrl(self.mac_ctrl)
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def set_loopback(self, enable):
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" Enable or disable Aurora loopback mode "
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if enable:
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self.log.info("Enable Aurora loopback")
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self.mac_ctrl = self.mac_ctrl | 0b100
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else:
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self.log.info("Disable Aurora loopback")
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self.mac_ctrl = self.mac_ctrl & 0xFFFFFFFB
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self.set_mac_ctrl(self.mac_ctrl)
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def set_bist_rate(self, rate_word):
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" Set BIST rate. It's a 6-bit value in the MAC ctrl register. "
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self.log.debug("Setting Aurora BIST rate word to 0x{:02X}".format(
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rate_word
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))
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self.mac_ctrl = self.mac_ctrl | ((rate_word & 0x3F) << 3)
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self.set_mac_ctrl(self.mac_ctrl)
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def reset_phy(self):
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" Reset Aurora PHY "
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self.log.debug("Reset Aurora PHY")
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self.mac_ctrl = self.mac_ctrl | (1<<9)
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self.set_mac_ctrl(self.mac_ctrl)
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self.clear_control_reg()
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def clear_mac(self):
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" Clear Aurora MAC "
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self.log.debug("Clear Aurora MAC")
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self.mac_ctrl = self.mac_ctrl | (1<<10)
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self.set_mac_ctrl(self.mac_ctrl)
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self.clear_control_reg()
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def clear_control_reg(self):
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" Zero out Aurora control register "
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self.mac_ctrl = 0
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self.set_mac_ctrl(self.mac_ctrl)
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def get_rate_setting(self, requested_rate, bus_clk_rate):
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"""
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From a requested bit rate, return the value for the rate register, and
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the coerced value.
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"""
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max_rate_word = 2**self.RATE_RES_BITS - 1
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lines_per_clock = float(requested_rate) / 64 / bus_clk_rate
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rate_word = int(lines_per_clock * 2**self.RATE_RES_BITS) - 1
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rate_word = min(max(rate_word, 0), max_rate_word)
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coerced_rate = ((1+rate_word) / 2**self.RATE_RES_BITS) \
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* 64 * bus_clk_rate
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return rate_word, coerced_rate
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def is_phy_link_up(self):
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"""
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Return True if the PHY link was successfully negotiated.
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"""
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return bool(self.read_phy_ctrl_status() & 0x1)
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def reset_core(self):
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" Reset MAC. PHY reset not necessary"
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self.clear_control_reg()
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self.clear_mac()
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def run_latency_loopback_bist(
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self,
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duration,
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requested_rate,
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slave=None,
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):
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"""
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Run latency loopback BIST
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slave -- the other sfp core gets set to loopback mode
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ctrl -- sorta the master sfp core
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duration -- time we want to run the bist
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requested_rate -- Requested BIST rate in bits/s
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"""
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rate_word, coerced_rate = \
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self.get_rate_setting(requested_rate, self.bus_clk_rate)
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self.log.info(
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'Running Latency Loopback BIST at %.0fMB/s for %.0fs...',
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coerced_rate/8e6, duration
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)
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self._pre_test_init(slave)
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start_time = time.time()
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results = {
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'latencies': [],
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'mst_lock_errors': 0,
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'mst_hard_errors': 0,
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'mst_overruns': 0,
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}
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try:
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for _ in range(duration*10):
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self.set_bist_rate(rate_word)
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self.set_bist_checker_and_gen(enable=True)
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# Wait and check if BIST locked
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time.sleep(0.05)
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mst_status = self.read_mac_ctrl_status()
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if not mst_status & self.MAC_STATUS_BIST_LOCKED_MSK:
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results['mst_lock_errors'] += 1
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self.log.info('lock errors: %d', results['mst_lock_errors'])
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# Turn off the BIST generator
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self.set_bist_gen(0)
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# Validate status and no overruns
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mst_status = self.read_mac_ctrl_status()
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results['mst_overruns'] = self.read_overruns()
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if mst_status & self.MAC_STATUS_HARD_ERR_MSK:
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results['mst_hard_errors'] += 1
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time.sleep(0.05)
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self.clear_control_reg()
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# Compute latency
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results['latencies'].append(
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self._mst_status_to_latency_us(mst_status)
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)
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except KeyboardInterrupt:
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self.log.warning('Operation cancelled by user.')
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stop_time = time.time()
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# Report
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if results['mst_lock_errors'] > 0:
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self.log.error(
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'BIST engine did not lock onto a PRBS word %d times!',
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results['mst_lock_errors']
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)
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if results['mst_hard_errors'] > 0:
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self.log.error(
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'There were %d hard errors in master PHY',
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results['mst_hard_errors']
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)
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if results['mst_overruns'] > 0:
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self.log.error(
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'There were %d buffer overruns in master PHY',
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results['mst_overruns']
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)
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mu_lat = mean(results['latencies'])
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results['elapsed_time'] = stop_time - start_time
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self.log.info('BIST Complete!')
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self.log.info('- Elapsed Time = ' + str(results['elapsed_time']))
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self.log.info('- Roundtrip Latency Mean = %.2fus', mu_lat)
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self.log.info('- Roundtrip Latency Stdev = %.6fus',
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stddev(results['latencies'], mu=mu_lat))
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# Turn off BIST loopback
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time.sleep(0.5)
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if slave is not None:
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results['sla_overruns'], results['sla_hard_errors'] = \
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self._get_slave_status(slave)
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self._post_test_cleanup(slave)
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return results
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def run_ber_loopback_bist(self, duration, requested_rate, slave=None):
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"""
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Run BER Bist. Pump lots of bits through, and see how many come back
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correctly.
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duration -- Time to run the test in seconds
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"""
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rate_word, coerced_rate = \
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self.get_rate_setting(requested_rate, self.bus_clk_rate)
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self.log.info('Running BER Loopback BIST at {}MB/s for {}s...'.format(
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coerced_rate/8e6, duration
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))
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self._pre_test_init(slave)
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mst_overruns = 0
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self.log.info("Starting BER test...")
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start_time = time.time()
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self.set_bist_rate(rate_word)
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self.set_bist_checker_and_gen(enable=True)
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# Wait and check if BIST locked
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time.sleep(0.5)
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mst_status = self.read_mac_ctrl_status()
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if not mst_status & self.MAC_STATUS_BIST_LOCKED_MSK:
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error_msg = 'BIST engine did not lock onto a PRBS word! ' \
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'MAC status word: 0x{:08X}'.format(mst_status)
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self.log.error(error_msg)
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raise RuntimeError(error_msg)
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# Wait for requested time
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try:
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time.sleep(duration)
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except KeyboardInterrupt:
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self.log.warning('Operation cancelled by user.')
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# Turn off the BIST generator and loopback
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self.set_bist_gen(enable=False)
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results = {}
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results['time_elapsed'] = time.time() - start_time
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time.sleep(0.5)
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# Validate status and no overruns
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mst_status = self.read_mac_ctrl_status()
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results['mst_overruns'] = self.read_overruns()
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results['mst_samps'] = 65536 * self.read_bist_checker_samps()
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results['mst_errors'] = self.read_bist_checker_errors()
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if mst_status & self.MAC_STATUS_HARD_ERR_MSK:
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self.log.error('Hard errors in master PHY')
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results['mst_hard_errors'] = True
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if mst_overruns > 0:
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self.log.error('Buffer overruns in master PHY')
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if slave is not None:
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results['sla_overruns'], results['sla_hard_errors'] = \
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self._get_slave_status(slave)
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if results['mst_samps'] != 0:
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results['mst_latency_us'] = \
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self._mst_status_to_latency_us(mst_status)
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self.log.info('BIST Complete!')
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self.log.info('- Elapsed Time = {:.2} s'.format(
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results['time_elapsed']
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))
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results['max_ber'] = \
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float(results['mst_errors']+1) / results['mst_samps']
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results['approx_throughput'] = \
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(8 * results['mst_samps']) / results['time_elapsed']
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self.log.info('- Max BER (Bit Error Ratio) = %.4g ' \
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'(%d errors out of %d)',
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results['max_ber'],
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results['mst_errors'],
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results['mst_samps'])
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self.log.info('- Max Roundtrip Latency = %.1fus',
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results['mst_latency_us'])
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self.log.info('- Approx Throughput = %.0fMB/s',
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results['approx_throughput'] / 1e6)
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else:
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self.log.error('No samples received -- BIST Failed!')
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self._post_test_cleanup(slave)
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return results
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def _get_slave_status(self, slave):
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"""
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Read back status from the slave
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"""
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slave.clear_control_reg()
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sla_status = slave.read_mac_ctrl_status()
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sla_overruns = slave.read_overruns()
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sla_hard_errors = 0
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if sla_status & self.MAC_STATUS_HARD_ERR_MSK:
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self.log.error('Hard errors in slave PHY')
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sla_hard_errors = slave.read_overruns()
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if sla_overruns > 0:
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self.log.error('Buffer overruns in slave PHY')
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return sla_overruns, sla_hard_errors
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def _mst_status_to_latency_us(self, mst_status):
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" Convert a MAC status word into latency in microseconds "
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latency_cyc = 16.0 * \
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((mst_status & self.MAC_STATUS_BIST_LATENCY_MSK) \
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>> self.MAC_STATUS_BIST_LATENCY_OFFSET)
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return 1e6 * latency_cyc / self.bus_clk_rate
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def _pre_test_init(self, slave=None):
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" Set up core(s) for BISTing "
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self.reset_core()
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if slave is not None:
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slave.reset_core()
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time.sleep(1.5)
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if slave is not None:
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self.set_loopback(enable=False)
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slave.set_loopback(enable=True)
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self.log.debug("Status of PHY link: 0x{:08X}".format(
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self.read_phy_ctrl_status()
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))
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if not self.is_phy_link_up():
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raise RuntimeError("PHY link not up. Check connectors.")
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def _post_test_cleanup(self, slave=None):
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" Drain and Cleanup "
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self.log.info('Cleaning up...')
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self.set_bist_checker(enable=True)
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if slave is not None:
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slave.set_bist_checker(enable=True)
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time.sleep(0.5)
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self.clear_control_reg()
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if slave is not None:
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slave.clear_control_reg()
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