Wade Fife 3c3da4c62f fpga: lib: Add advanced features to IPv4 SV transport adapter ... This adds several features to the SystemVerilog Eth/IPv4/UDP transport adaptor including: - Compat register - NODE_INST register - Capabilities register - KV map access for custom routing on RX data paths - CHDR header removal for raw payloads to be sent over UDP Also adds xport_adapter_ctrl.py, which allows controlling the new registers. Co-authored-by: Martin Braun <martin.braun@ettus.com>		2022-08-29 17:01:45 -05:00
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pyusrp_periphs	n310: Add frontend bandwidth control	2022-04-07 13:28:02 -07:00
tests	mpm: Add CompatNumber utility class	2022-06-29 12:08:02 -07:00
usrp_mpm	fpga: lib: Add advanced features to IPv4 SV transport adapter	2022-08-29 17:01:45 -05:00
aurora_bist_test.py	mpm: n3xx: Fix usage of UIO in Aurora tests	2018-03-01 18:34:28 -08:00
CMakeLists.txt	debian: Update control and package building	2022-04-06 14:30:49 -07:00
copy_python_module.cmake	cmake: Update coding style to use lowercase commands	2018-11-14 14:10:09 -08:00
e320_bist	mpm: Fix units for DRAM BIST	2022-02-03 14:21:31 -06:00
n3xx_bist	mpm: n3xx: Recommend reboot USRP after BIST	2022-03-23 16:14:22 -05:00
setup.py.in	cmake: Add RegMaps build component to MPM	2021-03-01 15:57:01 -06:00
socket_test.py	mpm: Update all license headers	2018-02-19 16:55:08 -08:00
test_lmk.py	mpm: Update all license headers	2018-02-19 16:55:08 -08:00
usrp_hwd.py	sim: Integrate simulator into UHD	2020-10-28 15:25:48 -05:00
usrp_update_fs	mpm: Update usrp_update_fs to support X410	2021-07-08 00:05:43 -07:00
x4xx_bist	mpm: Add x4xx DRAM BIST	2022-02-03 14:21:31 -06:00