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876d4150aa
Note: template_lvbitx.{cpp,hpp} need to be excluded from the list of
files that clang-format gets applied against.
238 lines
8.3 KiB
C++
238 lines
8.3 KiB
C++
//
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// Copyright 2010-2012,2014 Ettus Research LLC
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// Copyright 2018 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: GPL-3.0-or-later
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//
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#include "codec_ctrl.hpp"
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#include "ad9777_regs.hpp"
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#include "ads62p44_regs.hpp"
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#include "usrp2_regs.hpp"
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#include <uhd/exception.hpp>
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#include <uhd/utils/log.hpp>
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#include <uhd/utils/safe_call.hpp>
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#include <stdint.h>
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using namespace uhd;
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usrp2_codec_ctrl::~usrp2_codec_ctrl(void)
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{
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/* NOP */
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}
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/*!
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* A usrp2 codec control specific to the ad9777 ic.
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*/
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class usrp2_codec_ctrl_impl : public usrp2_codec_ctrl
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{
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public:
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usrp2_codec_ctrl_impl(usrp2_iface::sptr iface, uhd::spi_iface::sptr spiface)
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{
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_iface = iface;
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_spiface = spiface;
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// setup the ad9777 dac
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_ad9777_regs.x_1r_2r_mode = ad9777_regs_t::X_1R_2R_MODE_1R;
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_ad9777_regs.filter_interp_rate = ad9777_regs_t::FILTER_INTERP_RATE_4X;
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_ad9777_regs.mix_mode = ad9777_regs_t::MIX_MODE_COMPLEX;
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_ad9777_regs.pll_divide_ratio = ad9777_regs_t::PLL_DIVIDE_RATIO_DIV1;
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_ad9777_regs.pll_state = ad9777_regs_t::PLL_STATE_ON;
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_ad9777_regs.auto_cp_control = ad9777_regs_t::AUTO_CP_CONTROL_AUTO;
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// I dac values
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_ad9777_regs.idac_fine_gain_adjust = 0;
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_ad9777_regs.idac_coarse_gain_adjust = 0xf;
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_ad9777_regs.idac_offset_adjust_lsb = 0;
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_ad9777_regs.idac_offset_adjust_msb = 0;
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// Q dac values
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_ad9777_regs.qdac_fine_gain_adjust = 0;
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_ad9777_regs.qdac_coarse_gain_adjust = 0xf;
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_ad9777_regs.qdac_offset_adjust_lsb = 0;
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_ad9777_regs.qdac_offset_adjust_msb = 0;
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// write all regs
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for (uint8_t addr = 0; addr <= 0xC; addr++) {
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this->send_ad9777_reg(addr);
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}
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set_tx_mod_mode(0);
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// power-up adc
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switch (_iface->get_rev()) {
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case usrp2_iface::USRP2_REV3:
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case usrp2_iface::USRP2_REV4:
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_iface->poke32(U2_REG_MISC_CTRL_ADC, U2_FLAG_MISC_CTRL_ADC_ON);
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break;
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case usrp2_iface::USRP_N200:
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case usrp2_iface::USRP_N210:
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_ads62p44_regs.reset = 1;
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this->send_ads62p44_reg(0x00); // issue a reset to the ADC
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// everything else should be pretty much default, i think
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//_ads62p44_regs.decimation = DECIMATION_DECIMATE_1;
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_ads62p44_regs.power_down = ads62p44_regs_t::POWER_DOWN_NORMAL;
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this->send_ads62p44_reg(0x14);
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this->set_rx_analog_gain(1);
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break;
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case usrp2_iface::USRP_N200_R4:
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case usrp2_iface::USRP_N210_R4:
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_ads62p44_regs.reset = 1;
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this->send_ads62p44_reg(0x00); // issue a reset to the ADC
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// everything else should be pretty much default, i think
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//_ads62p44_regs.decimation = DECIMATION_DECIMATE_1;
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_ads62p44_regs.override = 1;
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this->send_ads62p44_reg(0x14);
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_ads62p44_regs.power_down = ads62p44_regs_t::POWER_DOWN_NORMAL;
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_ads62p44_regs.output_interface = ads62p44_regs_t::OUTPUT_INTERFACE_LVDS;
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_ads62p44_regs.lvds_current = ads62p44_regs_t::LVDS_CURRENT_2_5MA;
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_ads62p44_regs.lvds_data_term = ads62p44_regs_t::LVDS_DATA_TERM_100;
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this->send_ads62p44_reg(0x11);
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this->send_ads62p44_reg(0x12);
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this->send_ads62p44_reg(0x14);
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this->set_rx_analog_gain(1);
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break;
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case usrp2_iface::USRP_NXXX:
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break;
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}
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}
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~usrp2_codec_ctrl_impl(void)
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{
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UHD_SAFE_CALL(
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// power-down dac
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_ad9777_regs.power_down_mode = 1; this->send_ad9777_reg(0);
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// power-down adc
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switch (_iface->get_rev()) {
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case usrp2_iface::USRP2_REV3:
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case usrp2_iface::USRP2_REV4:
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_iface->poke32(U2_REG_MISC_CTRL_ADC, U2_FLAG_MISC_CTRL_ADC_OFF);
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break;
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case usrp2_iface::USRP_N200:
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case usrp2_iface::USRP_N210:
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case usrp2_iface::USRP_N200_R4:
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case usrp2_iface::USRP_N210_R4:
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// send a global power-down to the ADC here... it will get lifted on
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// reset
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_ads62p44_regs.power_down = ads62p44_regs_t::POWER_DOWN_GLOBAL_PD;
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this->send_ads62p44_reg(0x14);
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break;
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case usrp2_iface::USRP_NXXX:
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break;
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})
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}
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void set_tx_mod_mode(int mod_mode)
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{
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// set the sign of the frequency shift
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_ad9777_regs.modulation_form = (mod_mode > 0)
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? ad9777_regs_t::MODULATION_FORM_E_PLUS_JWT
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: ad9777_regs_t::MODULATION_FORM_E_MINUS_JWT;
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// set the frequency shift
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switch (std::abs(mod_mode)) {
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case 0:
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case 1:
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_ad9777_regs.modulation_mode = ad9777_regs_t::MODULATION_MODE_NONE;
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break;
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case 2:
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_ad9777_regs.modulation_mode = ad9777_regs_t::MODULATION_MODE_FS_2;
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break;
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case 4:
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_ad9777_regs.modulation_mode = ad9777_regs_t::MODULATION_MODE_FS_4;
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break;
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case 8:
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_ad9777_regs.modulation_mode = ad9777_regs_t::MODULATION_MODE_FS_8;
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break;
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default:
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throw uhd::value_error("unknown modulation mode for ad9777");
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}
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this->send_ad9777_reg(0x01); // set the register
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}
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void set_rx_digital_gain(double gain)
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{ // fine digital gain
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switch (_iface->get_rev()) {
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case usrp2_iface::USRP_N200:
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case usrp2_iface::USRP_N210:
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case usrp2_iface::USRP_N200_R4:
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case usrp2_iface::USRP_N210_R4:
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_ads62p44_regs.fine_gain = int(gain / 0.5);
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this->send_ads62p44_reg(0x17);
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break;
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default:
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UHD_THROW_INVALID_CODE_PATH();
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}
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}
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void set_rx_digital_fine_gain(double gain)
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{ // gain correction
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switch (_iface->get_rev()) {
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case usrp2_iface::USRP_N200:
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case usrp2_iface::USRP_N210:
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case usrp2_iface::USRP_N200_R4:
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case usrp2_iface::USRP_N210_R4:
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_ads62p44_regs.gain_correction = int(gain / 0.05);
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this->send_ads62p44_reg(0x1A);
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break;
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default:
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UHD_THROW_INVALID_CODE_PATH();
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}
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}
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void set_rx_analog_gain(bool /*gain*/)
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{ // turns on/off analog 3.5dB preamp
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switch (_iface->get_rev()) {
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case usrp2_iface::USRP_N200:
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case usrp2_iface::USRP_N210:
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case usrp2_iface::USRP_N200_R4:
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case usrp2_iface::USRP_N210_R4:
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_ads62p44_regs.coarse_gain = ads62p44_regs_t::
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COARSE_GAIN_3_5DB; // gain ? ads62p44_regs_t::COARSE_GAIN_3_5DB :
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// ads62p44_regs_t::COARSE_GAIN_0DB;
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this->send_ads62p44_reg(0x14);
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break;
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default:
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UHD_THROW_INVALID_CODE_PATH();
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}
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}
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size_t get_tx_interpolation() const
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{
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return 4;
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}
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private:
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ad9777_regs_t _ad9777_regs;
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ads62p44_regs_t _ads62p44_regs;
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usrp2_iface::sptr _iface;
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uhd::spi_iface::sptr _spiface;
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void send_ad9777_reg(uint8_t addr)
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{
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uint16_t reg = _ad9777_regs.get_write_reg(addr);
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UHD_LOG_TRACE("USRP2", "send_ad9777_reg: 0x" << std::hex << reg);
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_spiface->write_spi(SPI_SS_AD9777, spi_config_t::EDGE_RISE, reg, 16);
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}
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void send_ads62p44_reg(uint8_t addr)
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{
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uint16_t reg = _ads62p44_regs.get_write_reg(addr);
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_spiface->write_spi(SPI_SS_ADS62P44, spi_config_t::EDGE_FALL, reg, 16);
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}
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};
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/***********************************************************************
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* Public make function for the usrp2 codec control
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**********************************************************************/
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usrp2_codec_ctrl::sptr usrp2_codec_ctrl::make(
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usrp2_iface::sptr iface, uhd::spi_iface::sptr spiface)
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{
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return sptr(new usrp2_codec_ctrl_impl(iface, spiface));
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}
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