mirror of
https://github.com/saymrwulf/uhd.git
synced 2026-05-15 21:01:26 +00:00
a252a2f3d8
No functional changes. Fixes for things that PyLint complains about, but are safe to change anyway, as well as a minor improvement to a docstring that referenced non-existant args. This touches files that are mpm.conf-related.
355 lines
13 KiB
Python
355 lines
13 KiB
Python
#
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# Copyright 2018 Ettus Research, a National Instruments Company
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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E320 peripherals
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"""
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import math
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from usrp_mpm.sys_utils.sysfs_gpio import SysFSGPIO, GPIOBank
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from usrp_mpm.periph_manager.common import MboardRegsCommon
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# Map register values to SFP transport types
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E320_SFP_TYPES = {
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0: "", # Port not connected
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1: "1G",
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2: "10G",
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3: "A", # Aurora
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}
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E320_FPGA_TYPES_BY_SFP = {
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(""): "",
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("1G"): "1G",
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("10G"): "XG",
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("A"): "AA",
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}
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class FrontpanelGPIO(GPIOBank):
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"""
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Abstraction layer for the front panel GPIO
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"""
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EMIO_BASE = 54
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FP_GPIO_OFFSET = 32 # Bit offset within the ps_gpio_* pins
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def __init__(self, ddr):
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GPIOBank.__init__(
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self,
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{'label': 'zynq_gpio'},
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self.FP_GPIO_OFFSET + self.EMIO_BASE,
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0xFF, # use_mask
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ddr
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)
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class MboardRegsControl(MboardRegsCommon):
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"""
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Control the FPGA Motherboard registers
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"""
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# pylint: disable=bad-whitespace
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# Motherboard registers
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MB_CLOCK_CTRL = 0x0018
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MB_XADC_RB = 0x001C
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MB_BUS_CLK_RATE = 0x0020
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MB_BUS_COUNTER = 0x0024
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MB_SFP_PORT_INFO = 0x0028
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MB_GPIO_CTRL = 0x002C
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MB_GPIO_MASTER = 0x0030
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MB_GPIO_RADIO_SRC = 0x0034
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MB_GPS_CTRL = 0x0038
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MB_GPS_STATUS = 0x003C
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MB_DBOARD_CTRL = 0x0040
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MB_DBOARD_STATUS = 0x0044
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# pylint: enable=bad-whitespace
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# Bitfield locations for the MB_CLOCK_CTRL register.
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MB_CLOCK_CTRL_PPS_SEL_INT = 0
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MB_CLOCK_CTRL_PPS_SEL_EXT = 1
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MB_CLOCK_CTRL_REF_SEL = 2
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MB_CLOCK_CTRL_REF_CLK_LOCKED = 3
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# Bitfield locations for the MB_GPIO_CTRL register.
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MB_GPIO_CTRL_BUFFER_OE_N = 0
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MB_GPIO_CTRL_EN_VAR_SUPPLY = 1
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MB_GPIO_CTRL_EN_2V5 = 2
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MB_GPIO_CTRL_EN_3V3 = 3
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# Bitfield locations for the MB_GPS_CTRL register.
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MB_GPS_CTRL_PWR_EN = 0
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MB_GPS_CTRL_RST_N = 1
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MB_GPS_CTRL_INITSURV_N = 2
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# Bitfield locations for the MB_GPS_STATUS register.
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MB_GPS_STATUS_LOCK = 0
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MB_GPS_STATUS_ALARM = 1
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MB_GPS_STATUS_PHASELOCK = 2
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MB_GPS_STATUS_SURVEY = 3
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MB_GPS_STATUS_WARMUP = 4
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# Bitfield locations for the MB_DBOARD_CTRL register.
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MB_DBOARD_CTRL_MIMO = 0
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MB_DBOARD_CTRL_TX_CHAN_SEL = 1
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# Bitfield locations for the MB_DBOARD_STATUS register.
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MB_DBOARD_STATUS_RX_LOCK = 6
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MB_DBOARD_STATUS_TX_LOCK = 7
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def __init__(self, label, log):
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MboardRegsCommon.__init__(self, label, log)
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def enable_fp_gpio(self, enable):
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""" Enable front panel GPIO buffers and power supply
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and set voltage 3.3 V
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"""
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self.set_fp_gpio_voltage(3.3)
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mask = 0xFFFFFFFF ^ ((0b1 << self.MB_GPIO_CTRL_BUFFER_OE_N) | \
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(0b1 << self.MB_GPIO_CTRL_EN_VAR_SUPPLY))
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with self.regs:
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reg_val = self.peek32(self.MB_GPIO_CTRL) & mask
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reg_val = reg_val | (not enable << self.MB_GPIO_CTRL_BUFFER_OE_N) | \
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(enable << self.MB_GPIO_CTRL_EN_VAR_SUPPLY)
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self.log.trace("Writing MB_GPIO_CTRL to 0x{:08X}".format(reg_val))
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return self.poke32(self.MB_GPIO_CTRL, reg_val)
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def set_fp_gpio_voltage(self, value):
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""" Set Front Panel GPIO voltage (in volts)
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3V3 2V5 | Voltage
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-----------------
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0 0 | 1.8 V
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0 1 | 2.5 V
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1 0 | 3.3 V
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Arguments:
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value : 3.3
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"""
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assert any([math.isclose(value, nn, abs_tol=0.1) for nn in (3.3,)]),\
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"FP GPIO currently only supports 3.3V"
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if math.isclose(value, 1.8, abs_tol=0.1):
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voltage_reg = 0
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elif math.isclose(value, 2.5, abs_tol=0.1):
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voltage_reg = 1
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elif math.isclose(value, 3.3, abs_tol=0.1):
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voltage_reg = 2
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mask = 0xFFFFFFFF ^ ((0b1 << self.MB_GPIO_CTRL_EN_3V3) | \
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(0b1 << self.MB_GPIO_CTRL_EN_2V5))
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with self.regs:
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reg_val = self.peek32(self.MB_GPIO_CTRL) & mask
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reg_val = reg_val | (voltage_reg << self.MB_GPIO_CTRL_EN_2V5)
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self.log.trace("Writing MB_GPIO_CTRL to 0x{:08X}".format(reg_val))
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return self.poke32(self.MB_GPIO_CTRL, reg_val)
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def get_fp_gpio_voltage(self):
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"""
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Get Front Panel GPIO voltage (in volts)
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"""
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mask = 0x3 << self.MB_GPIO_CTRL_EN_2V5
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voltage = [1.8, 2.5, 3.3]
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with self.regs:
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reg_val = (self.peek32(self.MB_GPIO_CTRL) & mask) >> self.MB_GPIO_CTRL_EN_2V5
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return voltage[reg_val]
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def set_fp_gpio_master(self, value):
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"""set driver for front panel GPIO
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Arguments:
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value {unsigned} -- value is a single bit bit mask of 8 pins GPIO
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"""
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with self.regs:
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self.poke32(self.MB_GPIO_MASTER, value)
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def get_fp_gpio_master(self):
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"""get "who" is driving front panel gpio
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The return value is a bit mask of 8 pins GPIO.
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0: means the pin is driven by PL
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1: means the pin is driven by PS
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"""
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with self.regs:
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return self.peek32(self.MB_GPIO_MASTER) & 0xff
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def set_fp_gpio_radio_src(self, value):
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"""set driver for front panel GPIO
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Arguments:
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value {unsigned} -- value is 2-bit bit mask of 8 pins GPIO
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00: means the pin is driven by radio 0
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01: means the pin is driven by radio 1
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"""
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with self.regs:
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self.poke32(self.MB_GPIO_RADIO_SRC, value)
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def get_fp_gpio_radio_src(self):
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"""get which radio is driving front panel gpio
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The return value is 2-bit bit mask of 8 pins GPIO.
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00: means the pin is driven by radio 0
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01: means the pin is driven by radio 1
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"""
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with self.regs:
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return self.peek32(self.MB_GPIO_RADIO_SRC) & 0xffff
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def set_time_source(self, time_source, ref_clk_freq):
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"""
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Set time source
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"""
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pps_sel_val = 0x0
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if time_source == 'internal' or time_source == 'gpsdo':
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self.log.trace("Setting time source to internal (GPSDO)"
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"({:.1f} MHz reference)...".format(ref_clk_freq))
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pps_sel_val = 0b1 << self.MB_CLOCK_CTRL_PPS_SEL_INT
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elif time_source == 'external':
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self.log.debug("Setting time source to external...")
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pps_sel_val = 0b1 << self.MB_CLOCK_CTRL_PPS_SEL_EXT
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else:
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assert False, "Cannot set to invalid time source: {}".format(time_source)
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pps_sel_mask = ((0b1 << self.MB_CLOCK_CTRL_PPS_SEL_INT) |
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(0b1 << self.MB_CLOCK_CTRL_PPS_SEL_EXT))
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with self.regs:
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# prevent glitches by writing a cleared value first, then the final value.
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reg_val = self.peek32(self.MB_CLOCK_CTRL) & ~pps_sel_mask
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self.log.trace("Writing MB_CLOCK_CTRL to 0x{:08X}".format(reg_val))
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self.poke32(self.MB_CLOCK_CTRL, reg_val)
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reg_val = reg_val | pps_sel_val
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self.log.trace("Writing MB_CLOCK_CTRL to 0x{:08X}".format(reg_val))
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self.poke32(self.MB_CLOCK_CTRL, reg_val)
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def set_clock_source(self, clock_source, ref_clk_freq):
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"""
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Set clock source
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"""
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if clock_source == 'internal' or clock_source == 'gpsdo':
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self.log.trace("Setting clock source to internal (GPSDO)"
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"({:.1f} MHz reference)...".format(ref_clk_freq))
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ref_sel_val = 0b0
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elif clock_source == 'external':
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self.log.debug("Setting clock source to external..."
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"({:.1f} MHz reference)...".format(ref_clk_freq))
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ref_sel_val = 0b1
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else:
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assert False, "Cannot set to invalid clock source: {}".format(clock_source)
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mask = 0xFFFFFFFF ^ (0b1 << self.MB_CLOCK_CTRL_REF_SEL)
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with self.regs:
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reg_val = self.peek32(self.MB_CLOCK_CTRL) & mask
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reg_val = reg_val | (ref_sel_val << self.MB_CLOCK_CTRL_REF_SEL)
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self.log.trace("Writing MB_CLOCK_CTRL to 0x{:08X}".format(reg_val))
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self.poke32(self.MB_CLOCK_CTRL, reg_val)
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def get_fpga_type(self):
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"""
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Reads the type of the FPGA image currently loaded
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Returns a string with the type (ie 1G, XG, AU, etc.)
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"""
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with self.regs:
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sfp_info_rb = self.peek32(self.MB_SFP_PORT_INFO)
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# Print the registers values as 32-bit hex values
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self.log.trace("SFP Info: 0x{0:0{1}X}".format(sfp_info_rb, 8))
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sfp_type = E320_SFP_TYPES.get((sfp_info_rb & 0x0000FF00) >> 8, "")
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self.log.trace("SFP type: {}".format(sfp_type))
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try:
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return E320_FPGA_TYPES_BY_SFP[(sfp_type)]
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except KeyError:
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self.log.warning("Unrecognized SFP type: {}"
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.format(sfp_type))
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return ""
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def get_gps_locked_val(self):
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"""
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Get GPS LOCK status
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"""
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mask = 0b1 << self.MB_GPS_STATUS_LOCK
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with self.regs:
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reg_val = self.peek32(self.MB_GPS_STATUS) & mask
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gps_locked = reg_val & 0x1 #FIXME
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if gps_locked:
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self.log.trace("GPS locked!")
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# Can return this value because the gps_locked value is on the LSB
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return gps_locked
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def get_gps_status(self):
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"""
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Get GPS status
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"""
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mask = 0x1F
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with self.regs:
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gps_status = self.peek32(self.MB_GPS_STATUS) & mask
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return gps_status
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def enable_gps(self, enable):
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"""
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Turn power to the GPS (CLK_GPS_PWR_EN) off or on.
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Power signal is GPS_3V3.
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"""
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self.log.trace("{} power to GPS".format(
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"Enabling" if enable else "Disabling"
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))
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mask = 0xFFFFFFFF ^ (0b1 << self.MB_GPS_CTRL_PWR_EN)
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with self.regs:
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reg_val = self.peek32(self.MB_GPS_CTRL) & mask
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reg_val = reg_val | (enable << self.MB_GPS_CTRL_PWR_EN)
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self.log.trace("Writing MB_GPS_CTRL to 0x{:08X}".format(reg_val))
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return self.poke32(self.MB_GPS_CTRL, reg_val)
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def get_refclk_lock(self):
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"""
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Check the status of the reference clock (adf4002) in FPGA.
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"""
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mask = 0b1 << self.MB_CLOCK_CTRL_REF_CLK_LOCKED
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with self.regs:
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reg_val = self.peek32(self.MB_CLOCK_CTRL)
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locked = (reg_val & mask) > 0
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if not locked:
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self.log.warning("Reference Clock reporting unlocked. "
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"MB_CLOCK_CTRL reg: 0x{:08X}".format(reg_val))
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else:
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self.log.trace("Reference Clock locked!")
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return locked
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def set_channel_mode(self, channel_mode):
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"""
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Set channel mode in FPGA and select which tx channel to use
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channel mode = "MIMO" for mimo
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channel mode = "SISO_TX1", "SISO_TX0" for siso tx1, tx0 respectively.
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"""
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with self.regs:
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reg_val = self.peek32(self.MB_DBOARD_CTRL)
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if channel_mode == "MIMO":
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reg_val = (0b1 << self.MB_DBOARD_CTRL_MIMO)
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self.log.trace("Setting channel mode in AD9361 interface: %s",
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"2R2T" if channel_mode == 2 else "1R1T")
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else:
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# Warn if user tries to set either tx0/tx1 in mimo mode
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# as both will be set automatically
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if channel_mode == "SISO_TX1":
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# in SISO mode, Channel 1
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reg_val = (0b1 << self.MB_DBOARD_CTRL_TX_CHAN_SEL) | (0b0 << self.MB_DBOARD_CTRL_MIMO)
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self.log.trace("Setting TX channel in AD9361 interface to: TX1")
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elif channel_mode == "SISO_TX0":
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# in SISO mode, Channel 0
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reg_val = (0b0 << self.MB_DBOARD_CTRL_TX_CHAN_SEL) | (0b0 << self.MB_DBOARD_CTRL_MIMO)
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self.log.trace("Setting TX channel in AD9361 interface to: TX0")
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self.log.trace("Writing MB_DBOARD_CTRL to 0x{:08X}".format(reg_val))
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self.poke32(self.MB_DBOARD_CTRL, reg_val)
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def get_ad9361_tx_lo_lock(self):
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"""
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Check the status of TX LO lock from CTRL_OUT pins from Catalina
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"""
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mask = 0b1 << self.MB_DBOARD_STATUS_TX_LOCK
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with self.regs:
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reg_val = self.peek32(self.MB_DBOARD_STATUS)
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locked = (reg_val & mask) > 0
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if not locked:
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self.log.warning("TX RF PLL reporting unlocked. ")
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else:
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self.log.trace("TX RF PLL locked")
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return locked
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def get_ad9361_rx_lo_lock(self):
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"""
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Check the status of RX LO lock from CTRL_OUT pins from Catalina
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"""
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mask = 0b1 << self.MB_DBOARD_STATUS_RX_LOCK
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with self.regs:
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reg_val = self.peek32(self.MB_DBOARD_STATUS)
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locked = (reg_val & mask) > 0
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if not locked:
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self.log.warning("RX RF PLL reporting unlocked. ")
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else:
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self.log.trace("RX RF PLL locked")
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return locked
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