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458 lines
14 KiB
C
458 lines
14 KiB
C
// Copyright 2010-2012 Ettus Research LLC
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/*
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* Copyright 2007,2008,2009 Free Software Foundation, Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef INCLUDED_MEMORY_MAP_H
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#define INCLUDED_MEMORY_MAP_H
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#include <stdint.h>
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#define MASTER_CLK_RATE 100000000 // 100 MHz
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////////////////////////////////////////////////////////////////////////
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// Define slave bases
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////////////////////////////////////////////////////////////////////////
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#define ROUTER_RAM_BASE 0x4000
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#define SPI_BASE 0x5000
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#define I2C_BASE 0x5400
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#define GPIO_BASE 0x5800
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#define READBACK_BASE 0x5C00
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#define ETH_BASE 0x6000
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#define SETTING_REGS_BASE 0x7000
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#define PIC_BASE 0x8000
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#define UART_BASE 0x8800
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#define ATR_BASE 0x8C00
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#ifdef USRP2
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#define SDSPI_BASE 0xB000
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#endif
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#ifdef USRP2P
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#define ICAP_BASE 0xA000
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#define SPIF_BASE 0xB000
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#define RAM_BASE 0xC000
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#endif
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/////////////////////////////////////////////////////
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// SPI Core, Slave 2. See core docs for more info
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/////////////////////////////////////////////////////
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// Masks for controlling different peripherals
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#define SPI_SS_AD9510 1
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#define SPI_SS_AD9777 2
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#define SPI_SS_RX_DAC 4
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#define SPI_SS_RX_ADC 8
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#define SPI_SS_RX_DB 16
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#define SPI_SS_TX_DAC 32
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#define SPI_SS_TX_ADC 64
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#define SPI_SS_TX_DB 128
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#define SPI_SS_ADS62P44 256
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// Masks for different parts of CTRL reg
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#define SPI_CTRL_ASS (1<<13)
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#define SPI_CTRL_IE (1<<12)
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#define SPI_CTRL_LSB (1<<11)
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#define SPI_CTRL_TXNEG (1<<10)
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#define SPI_CTRL_RXNEG (1<< 9)
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#define SPI_CTRL_GO_BSY (1<< 8)
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#define SPI_CTRL_CHAR_LEN_MASK 0x7F
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////////////////////////////////////////////////
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// I2C, Slave 3
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////////////////////////////////////////////////
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typedef struct {
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volatile uint32_t prescaler_lo; // r/w
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volatile uint32_t prescaler_hi; // r/w
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volatile uint32_t ctrl; // r/w
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volatile uint32_t data; // wr = transmit reg; rd = receive reg
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volatile uint32_t cmd_status; // wr = command reg; rd = status reg
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} i2c_regs_t;
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#define i2c_regs ((i2c_regs_t *) I2C_BASE)
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#define I2C_CTRL_EN (1 << 7) // core enable
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#define I2C_CTRL_IE (1 << 6) // interrupt enable
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//
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// STA, STO, RD, WR, and IACK bits are cleared automatically
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//
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#define I2C_CMD_START (1 << 7) // generate (repeated) start condition
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#define I2C_CMD_STOP (1 << 6) // generate stop condition
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#define I2C_CMD_RD (1 << 5) // read from slave
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#define I2C_CMD_WR (1 << 4) // write to slave
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#define I2C_CMD_NACK (1 << 3) // when a rcvr, send ACK (ACK=0) or NACK (ACK=1)
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#define I2C_CMD_RSVD_2 (1 << 2) // reserved
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#define I2C_CMD_RSVD_1 (1 << 1) // reserved
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#define I2C_CMD_IACK (1 << 0) // set to clear pending interrupt
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#define I2C_ST_RXACK (1 << 7) // Received acknowledgement from slave (1 = NAK, 0 = ACK)
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#define I2C_ST_BUSY (1 << 6) // 1 after START signal detected; 0 after STOP signal detected
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#define I2C_ST_AL (1 << 5) // Arbitration lost. 1 when core lost arbitration
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#define I2C_ST_RSVD_4 (1 << 4) // reserved
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#define I2C_ST_RSVD_3 (1 << 3) // reserved
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#define I2C_ST_RSVD_2 (1 << 2) // reserved
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#define I2C_ST_TIP (1 << 1) // Transfer-in-progress
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#define I2C_ST_IP (1 << 0) // Interrupt pending
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///////////////////////////////////////////////////
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// Packet Router Status, Slave 5
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///////////////////////////////////////////////////
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typedef struct {
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volatile uint32_t spi;
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volatile uint32_t _padding[7];
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volatile uint32_t status;
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volatile uint32_t _unused;
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volatile uint32_t time64_secs_rb;
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volatile uint32_t time64_ticks_rb;
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volatile uint32_t compat_num;
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volatile uint32_t irqs;
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} router_status_t;
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#define SPI_READY_IRQ (1 << 12)
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#define router_status ((router_status_t *) READBACK_BASE)
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#define readback_mux ((router_status_t *) READBACK_BASE) //alias with a better name
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/*!
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* \brief return non-zero if we're running under the simulator
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*/
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inline static int
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hwconfig_simulation_p(void)
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{
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return 0;
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}
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/*!
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* \brief Return Wishbone Clock divisor.
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* The processor runs at the Wishbone Clock rate which is MASTER_CLK_RATE / divisor.
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*/
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inline static int
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hwconfig_wishbone_divisor(void)
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{
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return 2;
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}
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///////////////////////////////////////////////////
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// Ethernet Core, Slave 6
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///////////////////////////////////////////////////
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typedef struct {
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volatile int settings;
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volatile int ucast_hi;
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volatile int ucast_lo;
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volatile int mcast_hi;
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volatile int mcast_lo;
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volatile int miimoder;
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volatile int miiaddress;
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volatile int miitx_data;
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volatile int miicommand;
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volatile int miistatus;
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volatile int miirx_data;
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volatile int pause_time;
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volatile int pause_thresh;
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} eth_mac_regs_t;
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// settings register
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#define MAC_SET_PAUSE_EN (1 << 0) // Makes us respect received pause frames (normally on)
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#define MAC_SET_PASS_ALL (1 << 1) // Enables promiscuous mode, currently broken
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#define MAC_SET_PASS_PAUSE (1 << 2) // Sends pause frames through (normally off)
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#define MAC_SET_PASS_BCAST (1 << 3) // Sends broadcast frames through (normally on)
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#define MAC_SET_PASS_MCAST (1 << 4) // Sends multicast frames that match mcast addr (normally off)
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#define MAC_SET_PASS_UCAST (1 << 5) // Sends unicast (normal) frames through if they hit in address filter (normally on)
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#define MAC_SET_PAUSE_SEND_EN (1 << 6) // Enables sending pause frames
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// miicommand register
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#define MIIC_SCANSSTAT (1 << 0) // Scan status
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#define MIIC_RSTAT (1 << 1) // Read status
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#define MIIC_WCTRLDATA (1 << 2) // Write control data
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// miistatus register
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#define MIIS_LINKFAIL (1 << 0) // The link failed
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#define MIIS_BUSY (1 << 1) // The MII is busy (operation in progress)
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#define MIIS_NVALID (1 << 2) // The data in the status register is invalid
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// This it is only valid when the scan status is active.
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#define eth_mac ((eth_mac_regs_t *) ETH_BASE)
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////////////////////////////////////////////////////
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// Settings Bus, Slave #7, Not Byte Addressable!
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//
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// Output-only from processor point-of-view.
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// 1KB of address space (== 256 32-bit write-only regs)
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////////////////////////////////////////////////////
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#define SR_MISC 0 // 7 regs
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#define SR_SIMTIMER 8 // 2
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#define SR_TIME64 10 // 6
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#define SR_BUF_POOL 16 // 4
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#define SR_SPI_CORE 20 // 3
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#define SR_RX_FRONT 24 // 5
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#define SR_RX_CTRL0 32 // 9
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#define SR_RX_DSP0 48 // 7
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#define SR_RX_CTRL1 80 // 9
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#define SR_RX_DSP1 96 // 7
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#define SR_TX_FRONT 128 // ?
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#define SR_TX_CTRL 144 // 6
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#define SR_TX_DSP 160 // 5
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#define SR_UDP_SM 192 // 64
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#define _SR_ADDR(sr) (SETTING_REGS_BASE + (sr) * sizeof(uint32_t))
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#define SR_ADDR_BLDRDONE _SR_ADDR(5)
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// --- spi core control regs ---
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typedef struct {
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volatile uint32_t divider;
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volatile uint32_t control;
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volatile uint32_t data;
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} spi_core_t;
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#define SPI_CORE_SLAVE_SELECT_SHIFT 0
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#define SPI_CORE_NUM_BITS_SHIFT 24
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#define SPI_CORE_DATA_IN_EDGE_SHIFT 30
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#define SPI_CORE_DATA_OUT_EDGE_SHIFT 31
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#define spi_core ((spi_core_t *) _SR_ADDR(SR_SPI_CORE))
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// --- packet router control regs ---
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typedef struct {
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volatile uint32_t mode_ctrl;
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volatile uint32_t ip_addr;
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volatile uint32_t data_ports; //dsp0 (low 16) dsp1 (high 16)
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volatile uint32_t iface_ctrl;
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} router_ctrl_t;
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#define router_ctrl ((router_ctrl_t *) _SR_ADDR(SR_BUF_POOL))
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// --- misc outputs ---
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typedef struct {
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volatile uint32_t clk_ctrl;
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volatile uint32_t serdes_ctrl;
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volatile uint32_t adc_ctrl;
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volatile uint32_t leds;
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volatile uint32_t phy_ctrl; // LSB is reset line to eth phy
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volatile uint32_t debug_mux_ctrl;
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volatile uint32_t led_src; // HW or SW control for LEDs
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volatile uint32_t flush_icache; // Flush the icache
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} output_regs_t;
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#define CLK_RESET (1<<4)
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#define CLK_ENABLE (1<<3) | (1<<2)
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#define CLK_SEL (1<<1) | (1<<0)
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#define SERDES_ENABLE 8
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#define SERDES_PRBSEN 4
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#define SERDES_LOOPEN 2
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#define SERDES_RXEN 1
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#define ADC_CTRL_ON 0x0F
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#define ADC_CTRL_OFF 0x00
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// crazy order that matches the labels on the case
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#define LED_A (1 << 4)
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#define LED_B (1 << 1)
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#define LED_E (1 << 2)
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#define LED_D (1 << 0)
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#define LED_C (1 << 3)
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// LED_F // controlled by CPLD
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#define LED_RJ45 (1 << 5)
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#define output_regs ((output_regs_t *) SETTING_REGS_BASE)
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// --- protocol framer regs ---
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typedef struct{
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struct{
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volatile uint32_t entry[16];
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} table[4];
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} sr_proto_framer_t;
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#define sr_proto_framer_regs ((sr_proto_framer_t *) _SR_ADDR(SR_UDP_SM))
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// --- VITA TX CTRL regs ---
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typedef struct {
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volatile uint32_t _pad[4];
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volatile uint32_t cyc_per_up;
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} sr_tx_ctrl_t;
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#define sr_tx_ctrl ((sr_tx_ctrl_t *) _SR_ADDR(SR_TX_CTRL))
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// --- VITA RX CTRL regs ---
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typedef struct {
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volatile uint32_t _pad[8];
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volatile uint32_t clear;
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} sr_rx_ctrl_t;
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#define sr_rx_ctrl0 ((sr_rx_ctrl_t *) _SR_ADDR(SR_RX_CTRL0))
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#define sr_rx_ctrl1 ((sr_rx_ctrl_t *) _SR_ADDR(SR_RX_CTRL1))
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// ----------------------------------------------------------------
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// VITA49 64 bit time (write only)
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/*!
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* \brief Time 64 flags
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*
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* <pre>
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*
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* 3 2 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-----------------------------------------------------------+-+-+
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* | |S|P|
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* +-----------------------------------------------------------+-+-+
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*
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* P - PPS edge selection (0=negedge, 1=posedge, default=0)
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* S - Source (0=sma, 1=mimo, 0=default)
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*
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* </pre>
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*/
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typedef struct {
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volatile uint32_t secs; // value to set absolute secs to on next PPS
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volatile uint32_t ticks; // value to set absolute ticks to on next PPS
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volatile uint32_t flags; // flags - see chart above
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volatile uint32_t imm; // set immediate (0=latch on next pps, 1=latch immediate, default=0)
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} sr_time64_t;
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#define sr_time64 ((sr_time64_t *) _SR_ADDR(SR_TIME64))
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///////////////////////////////////////////////////////
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// Simple Programmable Interrupt Controller, Slave 8
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///////////////////////////////////////////////////////
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// Interrupt request lines
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// Bit numbers (LSB == 0) that correpond to interrupts into PIC
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#define IRQ_BUFFER 0 // buffer manager
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#define IRQ_ONETIME 1
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#define IRQ_SPI 2
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#define IRQ_I2C 3
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#define IRQ_PHY 4 // ethernet PHY
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#define IRQ_UNDERRUN 5
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#define IRQ_OVERRUN 6
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#define IRQ_PPS 7 // pulse per second
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#define IRQ_UART_RX 8
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#define IRQ_UART_TX 9
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#define IRQ_SERDES 10
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#define IRQ_CLKSTATUS 11
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#define IRQ_PERIODIC 12
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#define IRQ_BUTTON 13
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#define IRQ_TO_MASK(x) (1 << (x))
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#define PIC_BUFFER_INT IRQ_TO_MASK(IRQ_BUFFER)
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#define PIC_ONETIME_INT IRQ_TO_MASK(IRQ_ONETIME)
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#define PIC_SPI_INT IRQ_TO_MASK(IRQ_SPI)
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#define PIC_I2C_INT IRQ_TO_MASK(IRQ_I2C)
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#define PIC_PHY_INT IRQ_TO_MASK(IRQ_PHY)
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#define PIC_UNDERRUN_INT IRQ_TO_MASK(IRQ_UNDERRUN)
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#define PIC_OVERRUN_INT IRQ_TO_MASK(IRQ_OVERRUN)
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#define PIC_PPS_INT IRQ_TO_MASK(IRQ_PPS)
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#define PIC_UART_RX_INT IRQ_TO_MASK(IRQ_UART_RX)
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#define PIC_UART_TX_INT IRQ_TO_MASK(IRQ_UART_TX)
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#define PIC_SERDES IRQ_TO_MASK(IRQ_SERDES)
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#define PIC_CLKSTATUS IRQ_TO_MASK(IRQ_CLKSTATUS)
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#define PIC_BUTTON IRQ_TO_MASK(IRQ_BUTTON)
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typedef struct {
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volatile uint32_t edge_enable; // mask: 1 -> edge triggered, 0 -> level
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volatile uint32_t polarity; // mask: 1 -> rising edge
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volatile uint32_t mask; // mask: 1 -> disabled
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volatile uint32_t pending; // mask: 1 -> pending; write 1's to clear pending ints
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} pic_regs_t;
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#define pic_regs ((pic_regs_t *) PIC_BASE)
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// ----------------------------------------------------------------
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// WB_CLK_RATE is the time base for this
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typedef struct {
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volatile uint32_t onetime; // Number of wb clk cycles till the onetime interrupt
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volatile uint32_t periodic; // Repeat rate of periodic interrupt
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} sr_simple_timer_t;
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#define sr_simple_timer ((sr_simple_timer_t *) _SR_ADDR(SR_SIMTIMER))
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///////////////////////////////////////////////////
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// UART, Slave 10
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///////////////////////////////////////////////////
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typedef struct {
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// All elements are 8 bits except for clkdiv (16), but we use uint32 to make
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// the hardware for decoding easier
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volatile uint32_t clkdiv; // Set to 50e6 divided by baud rate (no x16 factor)
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volatile uint32_t txlevel; // Number of spaces in the FIFO for writes
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volatile uint32_t rxlevel; // Number of available elements in the FIFO for reads
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volatile uint32_t txchar; // Write characters to be sent here
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volatile uint32_t rxchar; // Read received characters here
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volatile uint32_t padding[3]; //what is this i don't even
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} uart_regs_t;
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#define uart_regs ((uart_regs_t *) UART_BASE)
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///////////////////////////////////////////////////
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// SD Card SPI interface, Slave 13
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// All regs are 8 bits wide, but are accessed as if they are 32 bits
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///////////////////////////////////////////////////
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#ifdef USRP2
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typedef struct {
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volatile uint32_t status; // Write a 1 or 0 for controlling CS
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volatile uint32_t clkdiv;
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volatile uint32_t send_dat;
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volatile uint32_t receive_dat;
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} sdspi_regs_t;
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#define sdspi_regs ((sdspi_regs_t *) SDSPI_BASE)
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#endif //USRP2
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///////////////////////////////////////////////////
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// ICAP, Slave 13
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///////////////////////////////////////////////////
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#ifdef USRP2P
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typedef struct {
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uint32_t icap; //only the lower 8 bits matter
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} icap_regs_t;
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#define icap_regs ((icap_regs_t *) ICAP_BASE)
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///////////////////////////////////////////////////
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// SPI Flash interface, Slave 14
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// Control register definitions are the same as SPI, so use SPI_CTRL_ASS, etc.
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// Peripheral mask not needed since bus is dedicated (CE held low)
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///////////////////////////////////////////////////
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typedef struct {
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volatile uint32_t txrx0;
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volatile uint32_t txrx1;
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volatile uint32_t txrx2;
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volatile uint32_t txrx3;
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volatile uint32_t ctrl;
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volatile uint32_t div;
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volatile uint32_t ss;
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} spif_regs_t;
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#define spif_regs ((spif_regs_t *) SPIF_BASE)
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#endif //USRP2P
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#endif /* INCLUDED_MEMORY_MAP_H */
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