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https://github.com/saymrwulf/uhd.git
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e244764ffa
The pca953x driver introduced a change for how the "label" property
populates. Instead of using the device model, it gives a device specific
name. As a replacement, use device/name. This affects the tca6424
and tca6408.
For the kernel change that causes this see:
5128f8d445
277 lines
8.7 KiB
Python
277 lines
8.7 KiB
Python
#
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# Copyright 2018 Ettus Research, a National Instruments Company
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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Rhodium dboard peripherals (CPLD, port expander, dboard regs)
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"""
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import time
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from usrp_mpm.sys_utils.sysfs_gpio import SysFSGPIO, GPIOBank, find_gpio_device
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from usrp_mpm.mpmutils import poll_with_timeout
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class TCA6408(object):
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"""
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Abstraction layer for the port/gpio expander
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"""
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pins = (
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'PWR-GOOD-3.6V', #3.6V
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'PWR-GOOD-1.1V', #1.1V
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'PWR-GOOD-2.0V', #2.0V
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'PWR-GOOD-5.4V', #5.4V
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'PWR-GOOD-5.5V', #6.8V
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)
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def __init__(self, i2c_dev):
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assert i2c_dev is not None
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self._gpios = SysFSGPIO({'device/name': 'tca6408'}, 0x3F, 0x00, 0x00, i2c_dev)
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def set(self, name, value=None):
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"""
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Assert a pin by name
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"""
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assert name in self.pins
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self._gpios.set(self.pins.index(name), value=value)
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def reset(self, name):
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"""
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Deassert a pin by name
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"""
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self.set(name, value=0)
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def get(self, name):
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"""
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Read back a pin by name
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"""
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assert name in self.pins
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return self._gpios.get(self.pins.index(name))
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class FPGAtoLoDist(object):
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"""
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Abstraction layer for the port/gpio expander on the LO Distribution board
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"""
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EXPECTED_BOARD_REV = 0
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POWER_ON_TIMEOUT = 20 #ms
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POWER_ON_POLL_INTERVAL = 1 #ms
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GPIO_DEV_ID = {
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'device/name': 'tca6424',
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'device/of_node/name': 'rhodium-lodist-gpio',
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}
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pins = (
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'BD_REV_0', #Board revision bit 0
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'BD_REV_1', #Board revision bit 1
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'BD_REV_2', #Board revision bit 2
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'P6_8V_PG', #6.8V Power good
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'4', #No connect
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'5', #No connect
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'6', #No connect
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'7', #No connect
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'RX_OUT0_CTRL', #RX Out0 Port Termination Switch
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'RX_OUT1_CTRL', #RX Out1 Port Termination Switch
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'RX_OUT2_CTRL', #RX Out2 Port Termination Switch
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'RX_OUT3_CTRL', #RX Out3 Port Termination Switch
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'RX_INSWITCH_CTRL', #RX 1:4 splitter input select
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'TX_OUT0_CTRL', #TX Out0 Port Termination Switch
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'TX_OUT1_CTRL', #TX Out1 Port Termination Switch
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'TX_OUT2_CTRL', #TX Out2 Port Termination Switch
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'TX_OUT3_CTRL', #TX Out3 Port Termination Switch
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'TX_INSWITCH_CTRL', #TX 1:4 splitter input select
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'P6_8V_EN', #6.8V supply enable
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'P6_5V_LDO_EN', #6.5V LDO enable
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'P3_3V_RF_EN' #3.3V LDO for RF enable
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)
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@staticmethod
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def lo_dist_present(i2c_dev):
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"""
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Returns True if the I2C board is present.
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"""
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dev, _ = find_gpio_device(FPGAtoLoDist.GPIO_DEV_ID, i2c_dev)
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return dev is not None
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def __init__(self, i2c_dev):
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assert i2c_dev is not None
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self._gpios = \
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SysFSGPIO(self.GPIO_DEV_ID, 0x1FFF0F, 0x1FFF00, 0x00A500, i2c_dev)
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board_rev = self._gpios.get(self.pins.index('BD_REV_0')) + \
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self._gpios.get(self.pins.index('BD_REV_1')) << 1 + \
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self._gpios.get(self.pins.index('BD_REV_2')) << 2
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if board_rev != self.EXPECTED_BOARD_REV:
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raise RuntimeError(
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'LO distribution board revision did not match: '
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'Expected: {0} Actual: {1}'
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.format(self.EXPECTED_BOARD_REV, board_rev))
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self._gpios.set(self.pins.index('P6_8V_EN'), 1)
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if not poll_with_timeout(
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lambda: bool(self._gpios.get(self.pins.index('P6_8V_PG'))),
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self.POWER_ON_TIMEOUT,
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self.POWER_ON_POLL_INTERVAL):
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self._gpios.set(self.pins.index('P6_8V_EN'), 0)
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raise RuntimeError('Power on failure for LO Distribution board')
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self._gpios.set(self.pins.index('P6_5V_LDO_EN'), 1)
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self._gpios.set(self.pins.index('P3_3V_RF_EN'), 1)
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def set(self, name, value=None):
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"""
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Assert a pin by name
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"""
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assert name in self.pins
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self._gpios.set(self.pins.index(name), value=value)
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def reset(self, name):
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"""
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Deassert a pin by name
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"""
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assert name in self.pins
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self.set(name, value=0)
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def get(self, name):
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"""
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Read back a pin by name
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"""
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assert name in self.pins
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return self._gpios.get(self.pins.index(name))
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class FPGAtoDbGPIO(GPIOBank):
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"""
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Abstraction layer for the FPGA to Daughterboard GPIO
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"""
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EMIO_BASE = 54+8
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DB_POWER_ENABLE = 0
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RF_POWER_ENABLE = 1
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def __init__(self, slot_idx):
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pwr_base = self.EMIO_BASE + 2*slot_idx
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GPIOBank.__init__(
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self,
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{'label': 'zynq_gpio'},
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pwr_base,
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0x3, # use_mask
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0x3, # ddr
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)
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class RhCPLD(object):
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"""
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Control class for the CPLD.
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"""
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REG_SIGNATURE = 0x0000
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REG_MINOR_REVISION = 0x0001
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REG_MAJOR_REVISION = 0x0002
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REG_BUILD_CODE_LSB = 0x0003
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REG_BUILD_CODE_MSB = 0x0004
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REG_SCRATCH = 0x0005
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REG_GAIN_TABLE_SEL = 0x0006
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REG_DAC_ALARM = 0x0007
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CPLD_SIGNATURE = 0x0045
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CPLD_MAJOR_REV = 4
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CPLD_MINOR_REV = 0
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def __init__(self, regs, log):
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"""
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Initialize communication with the Rh CPLD
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"""
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self.log = log.getChild("CPLD")
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self.log.debug("Initializing CPLD...")
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self.cpld_regs = regs
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self.poke16 = self.cpld_regs.peek16
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self.peek16 = self.cpld_regs.peek16
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# According to the datasheet, The CPLD's internal configuration time can take
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# anywhere from 0.6 to 3.4 ms. Until then, any ifc accesses will be invalid,
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# We will blind wait 5 ms and check the signature register to verify operation
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time.sleep(0.005)
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signature = self.peek16(self.REG_SIGNATURE)
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if self.CPLD_SIGNATURE != signature:
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self.log.error("CPLD Signature Mismatch! " \
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"Expected: 0x{:04X} Got: 0x{:04X}".format(self.CPLD_SIGNATURE, signature))
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raise RuntimeError("CPLD Signature Check Failed! "
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"Incorrect signature readback.")
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minor_rev = self.peek16(self.REG_MINOR_REVISION)
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major_rev = self.peek16(self.REG_MAJOR_REVISION)
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if major_rev != self.CPLD_MAJOR_REV:
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self.log.error(
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"CPLD Major Revision check mismatch! Expected: %d Got: %d",
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self.CPLD_MAJOR_REV,
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major_rev
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)
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raise RuntimeError("CPLD Revision Check Failed! MPM is not "
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"compatible with the loaded CPLD image.")
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date_code = self.peek16(self.REG_BUILD_CODE_LSB) | \
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(self.peek16(self.REG_BUILD_CODE_MSB) << 16)
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self.log.debug(
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"CPLD Signature: 0x{:04X} "
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"Revision: {}.{} "
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"Date code: 0x{:08X}"
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.format(signature, major_rev, minor_rev, date_code))
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def get_dac_alarm(self):
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"""
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This function polls and returns the DAC's ALARM signal connected to the CPLD.
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"""
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return (self.peek16(self.REG_DAC_ALARM) & 0x0001)
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class DboardClockControl(object):
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"""
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Control the FPGA MMCM for Radio Clock control.
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"""
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# Clocking Register address constants
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RADIO_CLK_MMCM = 0x0020
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PHASE_SHIFT_CONTROL = 0x0024
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RADIO_CLK_ENABLES = 0x0028
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MGT_REF_CLK_STATUS = 0x0030
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def __init__(self, regs, log):
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self.log = log
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self.regs = regs
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self.poke32 = self.regs.poke32
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self.peek32 = self.regs.peek32
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def enable_outputs(self, enable=True):
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"""
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Enables or disables the MMCM outputs.
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"""
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if enable:
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self.poke32(self.RADIO_CLK_ENABLES, 0x011)
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else:
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self.poke32(self.RADIO_CLK_ENABLES, 0x000)
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def reset_mmcm(self):
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"""
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Uninitialize and reset the MMCM
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"""
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self.log.trace("Disabling all Radio Clocks, then resetting MMCM...")
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self.enable_outputs(False)
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self.poke32(self.RADIO_CLK_MMCM, 0x1)
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def enable_mmcm(self):
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"""
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Unreset MMCM and poll lock indicators
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If MMCM is not locked after unreset, an exception is thrown.
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"""
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self.log.trace("Un-resetting MMCM...")
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self.poke32(self.RADIO_CLK_MMCM, 0x2)
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if not poll_with_timeout(
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lambda: bool(self.peek32(self.RADIO_CLK_MMCM) & 0x10),
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500,
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10,
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):
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self.log.error("MMCM not locked!")
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raise RuntimeError("MMCM not locked!")
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self.log.trace("MMCM locked. Enabling output MMCM clocks...")
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self.enable_outputs(True)
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def check_refclk(self):
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"""
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Not technically a clocking reg, but related.
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"""
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return bool(self.peek32(self.MGT_REF_CLK_STATUS) & 0x1)
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