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3760 commits 30 branches 147 tags 147 MiB
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550 commits

Author SHA1 Message Date
Josh Blum
672a77767f fifo ctrl: ~usrp2_fifo_ctrl acks, usrp2 DCM workaround, bootloader no blinkie 2012-03-23 14:36:56 -07:00
Josh Blum
12223186e7 fifo ctrl: spi core work and host implementation 2012-03-23 14:36:56 -07:00
Josh Blum
08e2432cde spi: work on fw support for simple spi core 2012-03-23 14:36:56 -07:00
Josh Blum
ee04c245f1 usrp2: permanent timeout increase for timed commands 2012-03-23 14:36:56 -07:00
Josh Blum
b1d82758b0 usrp2: implementation of timed commands working 2012-03-23 14:36:56 -07:00
Josh Blum
f59ef44a43 usrp2: integrated fifo ctrl into usrp2 modules, implemented window'd acking 2012-03-23 14:36:56 -07:00
Josh Blum
cda81f584c usrp2: added vrt pack/unpacker to fifo ctrl 2012-03-23 14:36:56 -07:00
Josh Blum
fe0a5162cd usrp2: host and fw implementation for fifo control 2012-03-23 14:36:55 -07:00
Josh Blum
e4d3f63ce0 usrp2: work on alternative stream destination 2012-03-23 14:36:21 -07:00
Josh Blum
f91e247da2 usrp: fix from "rev iq correction" 
Must zero out the default IQ correction to have zero effect by default.
 2012-03-16 09:04:44 -07:00
Josh Blum
027bc2c03d n2x0: adjustment for phase delay over mimo cable 2012-03-14 17:37:41 -07:00
Josh Blum
fedad06362 usrp2: device locking tweaks 
1) use bottom bit for force lock condition,
that way we never check the time after proper shutdown

2) dont allow lock condition under fpga compat mismatch
 2012-02-29 09:31:31 -08:00
Josh Blum
bd7e53d385 usrp: reset cordics on init after tick rate update 2012-02-28 13:35:50 -08:00
Josh Blum
2e85c4a2f1 usrp2: some tweaks to the device locking logic 2012-02-20 15:33:42 -08:00
Josh Blum
b1f34b4fd0 usrp2: added retry logic to control packets 2012-02-20 10:51:36 -08:00
Josh Blum
3060006b35 uhd: added async md user payload and common utils 2012-02-14 18:26:03 -08:00
Josh Blum
1151000340 uhd: various tweaks for compiler warns and valgrind 2012-02-09 17:59:48 -08:00
Josh Blum
5eec31fab4 dsp rework: implement 64 bit ticks, no seconds 2012-02-06 16:40:42 -08:00
Josh Blum
b7ff81c9a8 dsp rework: work on usb wrapper for smaller packets, large luts 2012-02-02 15:15:54 -08:00
Josh Blum
d27125b9ab dsp rework: account for no sid used in tx vita pkt 2012-02-01 09:48:28 -08:00
Josh Blum
d46c176af3 dsp rework: tx trailer, scaling work (peak) 2012-01-31 14:56:31 -08:00
Josh Blum
781cafa871 gen2: added user setting regs api and user core 2012-01-31 14:56:31 -08:00
Josh Blum
aa95e53a91 dsp rework: work on scaling and args parsing on RX and TX dsp 
This simplified some copy pasta in the io_impl.cpp files,
and adds a place for sc8 tx mode in the tx dsp core code.
 2012-01-31 14:56:31 -08:00
Josh Blum
8f25550d1a dsp rework: implemented new scalefactor in rx dsp core 2012-01-31 14:56:31 -08:00
Josh Blum
9f2aa9235f uhd: add samples per pkt option to rx streamer 2012-01-26 13:03:09 -08:00
Josh Blum
b8e41cbbc9 uhd: flush transport for new rx streamers 2012-01-23 13:03:09 -08:00
Nick Foster
4cb26d251d N210 R4 should be using LVDS TX clock, not CMOS. 2012-01-04 17:06:23 -08:00
Josh Blum
f2388c07ec usrp2: fw fix for hal_uart_getc_noblock return code 2012-01-04 10:26:00 -08:00
Josh Blum
9f0a1e3148 Merge branch 'network_foo' 2011-12-21 13:05:44 -08:00
Josh Blum
81289ab051 usrp: added underflow_policy to tx streamer args 2011-12-20 17:38:00 -08:00
Josh Blum
1fef438d8b usrp2: use the socket to determine the device addr 2011-12-20 14:37:05 -08:00
Ben Hilburn
f3654090d9 UHD will now print 'L' whenever a late packet is transmitted. 
This is similiar to printing 'U' and 'S'. This functionality is not yet
supported on the USRP1.
 2011-12-12 10:29:11 -08:00
Josh Blum
40c637bfb7 uhd: work with stream clearing 
dont clear when using the compat device API

tx clear also resets expected seqnum

tx clear on usrp2 resets flow control monitor
 2011-12-05 13:04:23 -08:00
Josh Blum
dac9a5001a usrp: clear dsp when making new streamer 2011-11-21 09:55:55 -08:00
Josh Blum
cfa3f8283b usrp: fixed default initialization of iq bal correction 2011-11-13 16:44:01 -08:00
Josh Blum
88e02e0d55 uhd: created rx IQ imbalance app to parallel tx 2011-11-11 16:06:50 -08:00
Josh Blum
8459432067 usrp: basically working iq cal on tx 2011-11-10 20:22:54 -08:00
Josh Blum
6f1f5f5fa2 usrp: added missing include for weak ptr 2011-11-08 12:27:37 -08:00
Josh Blum
7749b0f065 uhd: useful tweaks from user 2011-11-08 09:32:40 -08:00
Josh Blum
f1434d7c52 usrp2: fix channel mapping calculation 2011-11-07 15:10:19 -08:00
Josh Blum
d9035414a2 usrp: work on dboard code to use subtrees to populate frontend props 2011-11-07 11:20:04 -08:00
Josh Blum
8bb81824ea usrp: parse rx stream args scalar 2011-11-05 12:14:14 -07:00
Josh Blum
69adaee902 usrp2: reg map change for GPIO core 2011-11-03 21:00:07 -07:00
Josh Blum
fbc5b54f49 somebody made a typo 2011-11-03 20:37:14 -07:00
Josh Blum
dedfa65256 usrp: reorganize frontend paths in tree for correction stuff 2011-11-03 20:37:14 -07:00
Josh Blum
a626450892 usrp: prefer name iq_balance for api call 2011-11-03 20:37:13 -07:00
Josh Blum
bd08f403e3 usrp: register properties for correction and dc offset 2011-11-03 20:37:13 -07:00
Josh Blum
ae9e89d76b usrp: added get_tx/rx_rates 2011-11-03 20:37:13 -07:00
Josh Blum
c885da1138 uhd: renamed convert markup to format 
removed convert args

added simd level

got orc and neon updated
 2011-11-03 20:37:12 -07:00
Josh Blum
0946176f51 usrp1: got the 16Msps working (needed non hb-filter image) 2011-11-03 20:37:11 -07:00