Now checks the oldest-compat-rev register. Current rev is read out for
logging purposes.
Reviewed-by: Daniel Jepson <daniel.jepson@ettus.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
MPM will now no longer keep a SID framer variable.
Reviewed-by: Trung Tran <trung.tran@ettus.com>
Reviewed-by: Brent Stapleton <brent.stapleton@ettus.com>
The echo server was using the wrong socket options, allowing responses
to be fragmented. Since we use the echo server for MTU discovery, that
would have beaten the purpose.
Also includes minor formatting fixes.
This splits up the transport code in mpmd_impl across multiple classes
to properly leverage the request_xport/commit_xport API in MPM.
Different types of transport (UDP, liberio) use their own distinct
classes, which are generated dynamically on request.
This is a true refactoring despite the large amount of changes; there
are no functional differences.
Reviewed-By: Brent Stapleton <brent.stapleton@ettus.com>
Reviewed-By: Trung Tran <trung.tran@ettus.com>
Reviewed-By: Ashish Chaudhari <ashish.chaudhari@ettus.com>
On FPGA loads, when the periph_manager is respawned, this will now
clear the previously registered methods.
Reviewed-By: Brent Stapleton <brent.stapleton@ettus.com>
This will enumerate CHDR interfaces as late as possible, so that the
user changing the IP address will not affect operations. Note that IP
is considered static during a UHD session.
Refactoring to use the C++-based UIO objects. The Liberio and Ethernet
objects now open the UIO before using it, and close it once done.
Reviewed-By: Martin Braun <martin.braun@ettus.com>
- Moved nijesdcore to cores/
- Moved udev, net, dtoverlay, uio to sys_utils/
- Made all imports non-relative (except in __init__.py files)
- Removed some unnecessary imports
- Reordered some imports for Python conventions
- re-structured Magnesium.init_jesd() sequence to accomodate the reconfiguration
- added DRP access protocols to nijesdcore.py
- cleaned up a few comments and log statements in nijesdcore.py for flow
Reviewed-By: Martin Braun <martin.braun@ettus.com>
- complete time_source options to match updates to fpga registers
- add methods for each of the bitfields in the clock control register
- add init sequences for the meas_clk MMCM and PPS output
Reviewed-By: Martin Braun <martin.braun@ettus.com>
Current code have couple places that open pyroute2 without closing it.
That seems to cause the file descriptor leakage.
This change effectively fix the issue #1964
Zlib's crc32 outputs signed values in python2 and unsigned values in
python3. As per this page (https://docs.python.org/2/library/zlib.html)
0xffffffff can be AND'd to the result to get the same value between
Python versions
- ClockSynchronizer object has no more permanent lifetime
- DboardClockControl object lives within `with' statement
- dboard_ctrl_regs are limited to init()
Upon updating certain components (the FPGA, for example), the
Peripheral Manager is restarted, and the overlay is reapplied. In order
to facilitate this, the RPC server intercepts and handles the
update_component function.
Tested on the RJ45 ethernet connection. It probably won't work as well
if the SFP connection goes down when the overlay is removed.
Previously, the daughterboard requested an overlay file based on SFP
preference using magic values. This commit moves the decision making to
the peripheral manager, which uses our singular name (ie 'n3xx' for the
N310).
