mpm: apply linting on lmk04832.py

mpm/python/usrp_mpm/chips/lmk04832.py

@@ -8,12 +8,15 @@ LMK04832 parent driver class
 """
 
 import time
+
 from usrp_mpm.mpmlog import get_logger
 
+
 class LMK04832:
     """
     Generic driver class for LMK04832 access.
     """
+
     LMK_CHIP_ID = 6
     LMK_PROD_ID = 0xD163
 
@@ -24,15 +27,15 @@ class LMK04832:
     LMK_VCO1_RANGE_MAX = 3255e6
 
     # PLL2 Prescaler is in range from 2, 8
-    PLL2_PRESCALER = range(2,9)
+    PLL2_PRESCALER = range(2, 9)
 
     def __init__(self, regs_iface, parent_log=None):
-        self.log = \
-            parent_log.getChild("LMK04832") if parent_log is not None \
-            else get_logger("LMK04832")
+        self.log = (
+            parent_log.getChild("LMK04832") if parent_log is not None else get_logger("LMK04832")
+        )
         self.regs_iface = regs_iface
-        assert hasattr(self.regs_iface, 'peek8')
-        assert hasattr(self.regs_iface, 'poke8')
+        assert hasattr(self.regs_iface, "peek8")
+        assert hasattr(self.regs_iface, "poke8")
         self.poke8 = regs_iface.poke8
         self.peek8 = regs_iface.peek8
         self.enable_3wire_spi = False
@@ -59,8 +62,7 @@ class LMK04832:
         """
         prod_id_0 = self.peek8(0x04)
         prod_id_1 = self.peek8(0x05)
-        prod_id = (prod_id_1 << 8) \
-                  | prod_id_0
+        prod_id = (prod_id_1 << 8) | prod_id_0
         self.log.trace("Product ID Readback: 0x{:X}".format(prod_id))
         return prod_id
 
@@ -79,47 +81,41 @@ class LMK04832:
             return False
         return True
 
-
     def enable_4wire_spi(self):
-        """ Enable 4-wire SPI readback from the CLKin_SEL0 pin """
+        """Enable 4-wire SPI readback from the CLKin_SEL0 pin"""
         self.poke8(0x148, 0x33)
         self.enable_3wire_spi = False
 
-
     def get_status(self):
         """
         Returns PLL lock status as a dictionary
         """
-        pll1_status = self.check_plls_locked(pll='PLL1')
-        pll2_status = self.check_plls_locked(pll='PLL2')
-        return {'PLL1 lock': pll1_status,
-                'PLL2 lock': pll2_status}
+        pll1_status = self.check_plls_locked(pll="PLL1")
+        pll2_status = self.check_plls_locked(pll="PLL2")
+        return {"PLL1 lock": pll1_status, "PLL2 lock": pll2_status}
 
-
-    def check_plls_locked(self, pll='BOTH'):
+    def check_plls_locked(self, pll="BOTH"):
         """
         Returns True if the specified PLLs are locked, False otherwise.
         """
         pll = pll.upper()
-        assert pll in ('BOTH', 'PLL1', 'PLL2'), 'Invalid PLL specified'
+        assert pll in ("BOTH", "PLL1", "PLL2"), "Invalid PLL specified"
         result = True
         pll_lock_status = self.peek8(0x183)
 
-        if pll in ('BOTH', 'PLL1'):
+        if pll in ("BOTH", "PLL1"):
             # Lock status for PLL1 is 0x01 on bits [3:2]
             if (pll_lock_status & 0xC) != 0x04:
-                self.log.debug("PLL1 reporting unlocked... Status: 0x{:x}"
-                               .format(pll_lock_status))
+                self.log.debug("PLL1 reporting unlocked... Status: 0x{:x}".format(pll_lock_status))
                 result = False
-        if pll in ('BOTH', 'PLL2'):
+        if pll in ("BOTH", "PLL2"):
             # Lock status for PLL2 is 0x01 on bits [1:0]
             if (pll_lock_status & 0x3) != 0x01:
-                self.log.debug("PLL2 reporting unlocked... Status: 0x{:x}"
-                               .format(pll_lock_status))
+                self.log.debug("PLL2 reporting unlocked... Status: 0x{:x}".format(pll_lock_status))
                 result = False
         return result
 
-    def wait_for_pll_lock(self, pll='BOTH', timeout=2000):
+    def wait_for_pll_lock(self, pll="BOTH", timeout=2000):
         """
         Waits for the PLL(s) to lock.
         Returns False if the PLL(s) do not lock before the timeout (in ms)
@@ -133,8 +129,8 @@ class LMK04832:
             time.sleep(0.1)
             if self.check_plls_locked(pll):
                 return True
-        pll = 'PLL1 or PLL2' if pll.upper() == 'BOTH' else pll
-        self.log.debug('{} not reporting locked after {} ms wait'.format(pll, timeout))
+        pll = "PLL1 or PLL2" if pll.upper() == "BOTH" else pll
+        self.log.debug("{} not reporting locked after {} ms wait".format(pll, timeout))
         return False
 
     def soft_reset(self, value=True):
@@ -142,15 +138,14 @@ class LMK04832:
         Performs a soft reset of the LMK04832 by setting or unsetting the reset register.
         """
         reset_addr = 0
-        if value: # Reset
+        if value:  # Reset
             reset_byte = 0x80
-        else: # Clear Reset
+        else:  # Clear Reset
             reset_byte = 0x00
         if not self.enable_3wire_spi:
             reset_byte |= 0x10
         self.poke8(reset_addr, reset_byte)
 
-
     def pll1_r_divider_sync(self, sync_pin_callback):
         """
         Run PLL1 R Divider sync according to
@@ -195,11 +190,14 @@ class LMK04832:
         register fields.
         """
         # valid prescaler values are 2-8, where 8 is represented as 0x00.
-        assert prescaler in range(2, 8+1)
-        reg_val = ((prescaler & 0x07) << 5) \
-                  | ((osc_field & 0x3) << 2) \
-                  | ((xtal_en & 0x1) << 1) \
-                  | ((ref_2x_en & 0x1) << 0)
-        self.log.trace("From prescaler value 0d{}, writing register as 0x{:02X}."
-                       .format(prescaler, reg_val))
+        assert prescaler in range(2, 8 + 1)
+        reg_val = (
+            ((prescaler & 0x07) << 5)
+            | ((osc_field & 0x3) << 2)
+            | ((xtal_en & 0x1) << 1)
+            | ((ref_2x_en & 0x1) << 0)
+        )
+        self.log.trace(
+            "From prescaler value 0d{}, writing register as 0x{:02X}.".format(prescaler, reg_val)
+        )
         return reg_val