From c64b9e36cd2d4d2a2c21b1b94c613c300af0670e Mon Sep 17 00:00:00 2001 From: Martin Anderseck Date: Fri, 3 Nov 2023 16:00:58 +0100 Subject: [PATCH] mpm: Improve fall-back behavior for dual-rate This fixes the behavior that a non-valid dual-rate config could fall back to a single-rate configuration with two different converter rates. With this it also fixes the behavior that with those same master clock rates we wouldn't run mult-tile sync (as this depends on the converter rate). --- mpm/python/usrp_mpm/periph_manager/x4xx_clock_policy.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/mpm/python/usrp_mpm/periph_manager/x4xx_clock_policy.py b/mpm/python/usrp_mpm/periph_manager/x4xx_clock_policy.py index 2bb64d452..475a8456b 100644 --- a/mpm/python/usrp_mpm/periph_manager/x4xx_clock_policy.py +++ b/mpm/python/usrp_mpm/periph_manager/x4xx_clock_policy.py @@ -680,6 +680,8 @@ class X440ClockPolicy(X4xxClockPolicy): # Use the first MCR for both if we cannot combine them. if len(common_out) == 0: mcrs[1] = mcrs[0] + # Ensure we're falling back to converter rate 0, too + conv_rates[1] = conv_rates[0] # With these values check if we can do this in MMCM rfdc_rate = list(map(lambda x: int(x / (self._spc * self._extra_resampling)), mcrs)) @@ -687,6 +689,9 @@ class X440ClockPolicy(X4xxClockPolicy): # Inform user if we don't have an exact match if min_mmcm_vco_rate > X4xxRfdcCtrl.MMCM_VCO_MAX: mcrs[1] = mcrs[0] + # Ensure we're falling back to converter rate 0, too + conv_rates[1] = conv_rates[0] + if mcrs != master_clock_rates: self.log.warning(f"Unable to use desired master clock rate(s), using " f"{mcrs[0]/1e6} MHz for DB0 and {mcrs[1]/1e6} MHz for DB1.")