diff --git a/host/docs/usrp_b200.dox b/host/docs/usrp_b200.dox
index 95e9d4846..d4f505216 100644
--- a/host/docs/usrp_b200.dox
+++ b/host/docs/usrp_b200.dox
@@ -80,6 +80,19 @@ device arguments, which many applications take:
uhd_usrp_probe --args="master_clock_rate=52e6"
The property to control the master clock rate is a double value, called `tick_rate`.
+Example:
+
+~~~{.py}
+import uhd
+my_usrp = uhd.usrp.MultiUSRP("type=b200")
+# The following two lines are synonymous:
+my_usrp.set_master_clock_rate(16e6)
+my_usrp.get_tree().access_double('/mboards/0/tick_rate').set(16e6)
+# Note that if MCR changed, then all time-synchronization is lost!
+~~~
+
+Note that changing the master clock rate will reconfigure the entire clocking
+chain, thereby losing previous synchronization configurations.
\subsection b200_auto_mcr Automatic Clock Rate Setting
@@ -98,10 +111,28 @@ the largest possible clock rate as to enable as many half-band filters
as possible. Expert users might have cases where a more fine-grained
control over the resampling stages is required, in which case manually
selecting a master clock rate might be more suitable than the automatic
-rate.
+rate. Manual selection of master clock rate may also be required to synchronize
+multiple B200 units in time.
The property to dis- or enable the auto tick rate is a boolean value,
-`auto_tick_rate`.
+`auto_tick_rate`. Example:
+
+~~~{.py}
+>>> import uhd
+>>> my_usrp = uhd.usrp.MultiUSRP("type=b200")
+>>> my_usrp.get_tree().access_bool('/mboards/0/auto_tick_rate').get()
+True
+>>> my_usrp.set_master_clock_rate(16e6) # This will lock the MCR
+>>> my_usrp.get_tree().access_bool('/mboards/0/auto_tick_rate').get()
+False
+>>> U.set_rx_rate(7e6) # Not possible! We locked the MCR.
+>>> U.get_rx_rate() # The actual rate is coerced:
+8000000.0
+>>> my_usrp.get_tree().access_bool('/mboards/0/auto_tick_rate').set(True)
+>>> my_usrp.set_rx_rate(7e6) # This requires a new MCR...
+>>> my_usrp.get_master_clock_rate() # ...which is chosen automatically.
+56000000.0
+~~~
\section b200_fe RF Frontend Notes
@@ -297,13 +328,16 @@ Component ID | Description | Details
------------------------|----------------------------|---------------------------------------------------
J5021 | Mictor Connector | Interface to FPGA for I/O and inspection.
J5031 | JTAG Header | Interface to FPGA for programming and debugging.
- J5042 | GPIO Header | Header connected to the FPGA for GPIO purposes.
+ J5041,2 | GPIO Header | Header connected to the FPGA for GPIO purposes.
+ J4003 | GPIO/UART Header | Header connected to the FPGA for GPIO purposes, or as a serial interface to the FX3 (requires custom FPGA bitfile)
S700 | FX3 Hard Reset Switch | Resets the USB controller / System reset
U100 | GPSDO socket | Interface to GPS disciplined reference oscillator
1 Only on the B210
-2 Only since rev. 6 (green board). GPIO pinout is 1=GPIO_0, 2=GPIO_1, 3=GPIO_2, 4=GPIO_3, 5=GPIO_4, 6=GPIO_5, 7=GPIO_6, 8=GPIO_7, 9=GND, 10=GND
+2 Only since rev. 6 (green board). Default voltage is 3.3V. GPIO pinout is 1=GPIO_0, 2=GPIO_1, 3=GPIO_2, 4=GPIO_3, 5=GPIO_4, 6=GPIO_5, 7=GPIO_6, 8=GPIO_7, 9=GND, 10=GND
+
+3 Only since rev. 6 (green board). Default voltage is 1.8V. GPIO pinout is 1=GPIO_8, 2=GND, 3=GPIO_9. When compiling a bitfile to support a UART on this header, pinout is 1=TX, 2=GND, 3=RX.
Below is a table showing the B200mini on-board connectors and switches:
@@ -317,6 +351,9 @@ Component ID | Description | Details
\section b200_known_issues Known issues
+- When synchronizing multiple USRPs in time, it is strongly recommended to
+ specify a master clock rate instead of relying on \ref b200_auto_mcr.
+
- The B200 and B210 cannot support an external 10 MHz reference if a GPSDO is
already present on the motherboard. If an external 10 MHz reference is to be
used, the GPSDO needs to be physically removed from the device beforehand.