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X300: Reduce phase noise for 184.32 MHz MCR

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Reverts charge pump current changes for 10 MHz reference / 184.32 MHz
master clock rate case that caused additional phase noise.

Signed-off-by: michael-west <michael.west@ettus.com>
This commit is contained in:
michael-west 2021-03-18 11:49:20 -07:00 committed by Aaron Rossetto
parent 64ea8d91f8
commit bfbda2fb0d
1 changed files with 5 additions and 2 deletions
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7
host/lib/usrp/x300/x300_clock_ctrl.cpp
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@ -700,13 +700,16 @@ private:
// PLL1 - 2 MHz compare frequency
_lmk04816_regs.PLL1_N_28 = 48;
_lmk04816_regs.PLL1_R_27 = 5;
_lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_1600UA;
// Since this is not a zero-dealy mode, it is not intended for phase
// synchronization. The charge pump current for PLL1 is lowered to
// reduce phase noise.
_lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_100UA;
// PLL2 - 7.68 MHz compare frequency
_lmk04816_regs.PLL2_N_30 = 168;
_lmk04816_regs.PLL2_P_30 = lmk04816_regs_t::PLL2_P_30_DIV_2A;
_lmk04816_regs.PLL2_R_28 = 25;
_lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_100UA;
_lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_3200UA;
_lmk04816_regs.PLL2_R3_LF = lmk04816_regs_t::PLL2_R3_LF_4KILO_OHM;
_lmk04816_regs.PLL2_C3_LF = lmk04816_regs_t::PLL2_C3_LF_39PF;