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examples: Add IP to OOT RFNoC gain example
This updates the gain example to show how to use RFNoC IP, in-tree Xilinx IP, and out-of-tree Xilinx IP in a custom RFNoC block.
This commit is contained in:
Wade Fife
parent
866df135ad
commit
ada6a4e467
5 changed files with 335 additions and 39 deletions
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@ -6,16 +6,18 @@
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# We first need to figure out our own path, in case this file is being included
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# from somewhere else (e.g., from a fpgadev/top/$device directory)
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RFNOC_EXAMPLE_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
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OOT_FPGA_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
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# One include statement for every RFNoC block with its own subdirectory, which
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# itself will contain a Makefile.srcs
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include $(RFNOC_EXAMPLE_DIR)/rfnoc_block_gain/Makefile.srcs
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include $(OOT_FPGA_DIR)/rfnoc_block_gain/Makefile.srcs
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include $(OOT_FPGA_DIR)/ip/cmplx_mul/Makefile.inc
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LIB_IP_XCI_SRCS += $(LIB_IP_CMPLX_MUL_SRCS)
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# If there are additional modules or IP (other than what is in the RFNoC block
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# subdirectories) that needs to get installed in order to synthesize blocks from
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# this module, list them here:
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#RFNOC_OOT_SRCS += $(abspath $(addprefix ${RFNOC_EXAMPLE_DIR},
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#my_other_module.v \
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#ip/my_ip_core/my_ip_core.xci \
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#RFNOC_OOT_SRCS += $(abspath $(addprefix ${OOT_FPGA_DIR}, \
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#$(IP_BUILD_DIR)/cmplx_mul/cmplx_mul.xci \
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#))
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17
host/examples/rfnoc-example/fpga/ip/cmplx_mul/Makefile.inc
Normal file
17
host/examples/rfnoc-example/fpga/ip/cmplx_mul/Makefile.inc
Normal file
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@ -0,0 +1,17 @@
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#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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include $(TOOLS_DIR)/make/viv_ip_builder.mak
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LIB_IP_CMPLX_MUL_SRCS = $(IP_BUILD_DIR)/cmplx_mul/cmplx_mul.xci
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LIB_IP_CMPLX_MUL_OUTS = $(addprefix $(IP_BUILD_DIR)/cmplx_mul/, \
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cmplx_mul.xci.out \
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synth/cmplx_mul.vhd \
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)
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$(LIB_IP_CMPLX_MUL_SRCS) $(LIB_IP_CMPLX_MUL_OUTS) : $(OOT_FPGA_DIR)/ip/cmplx_mul/cmplx_mul.xci
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$(call BUILD_VIVADO_IP,cmplx_mul,$(ARCH),$(PART_ID),$(OOT_FPGA_DIR)/ip,$(IP_BUILD_DIR),0)
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187
host/examples/rfnoc-example/fpga/ip/cmplx_mul/cmplx_mul.xci
Normal file
187
host/examples/rfnoc-example/fpga/ip/cmplx_mul/cmplx_mul.xci
Normal file
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@ -0,0 +1,187 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>xci</spirit:library>
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<spirit:name>unknown</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:instanceName>cmplx_mul</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cmpy" spirit:version="6.0"/>
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.LAYERED_METADATA">undef</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.PHASE">0.000</spirit:configurableElementValue>
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
<spirit:vendorExtensions>
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||||
<xilinx:componentInstanceExtensions>
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||||
<xilinx:configElementInfos>
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||||
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST" xilinx:valueSource="auto"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY" xilinx:valueSource="auto"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB" xilinx:valueSource="constant"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH" xilinx:valueSource="constant"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH" xilinx:valueSource="constant"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TKEEP" xilinx:valueSource="constant"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TLAST" xilinx:valueSource="auto"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TREADY" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.HAS_TSTRB" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.TID_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TKEEP" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TLAST" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TREADY" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.HAS_TSTRB" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.TID_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TKEEP" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TREADY" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.HAS_TSTRB" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CTRL.TID_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARESETN" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FlowControl" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HasATLAST" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HasBTLAST" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MinimumLatency" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OptimizeGoal" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OutTLASTBehv" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
|
|
@ -19,24 +19,40 @@ include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
|
|||
#-------------------------------------------------
|
||||
# Design Specific
|
||||
#-------------------------------------------------
|
||||
|
||||
# In-tree IP
|
||||
LIB_IP_DIR = $(BASE_DIR)/../lib/ip
|
||||
include $(LIB_IP_DIR)/complex_multiplier/Makefile.inc
|
||||
|
||||
# Out-of-tree IP
|
||||
OOT_FPGA_DIR = $(dir $(abspath $(firstword $(MAKEFILE_LIST))))/../
|
||||
include $(OOT_FPGA_DIR)/ip/cmplx_mul/Makefile.inc
|
||||
|
||||
# Include makefiles and sources for the DUT and its
|
||||
# dependencies.
|
||||
include $(BASE_DIR)/../lib/rfnoc/Makefile.srcs
|
||||
include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
|
||||
include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
|
||||
include Makefile.srcs
|
||||
|
||||
DESIGN_SRCS += $(abspath \
|
||||
$(RFNOC_CORE_SRCS) \
|
||||
$(RFNOC_UTIL_SRCS) \
|
||||
$(RFNOC_OOT_SRCS) \
|
||||
DESIGN_SRCS += $(abspath \
|
||||
$(RFNOC_SRCS) \
|
||||
$(RFNOC_CORE_SRCS) \
|
||||
$(RFNOC_UTIL_SRCS) \
|
||||
$(RFNOC_OOT_SRCS) \
|
||||
$(LIB_IP_CMPLX_MUL_SRCS) \
|
||||
$(LIB_IP_COMPLEX_MULTIPLIER_SRCS) \
|
||||
)
|
||||
|
||||
#-------------------------------------------------
|
||||
# Testbench Specific
|
||||
#-------------------------------------------------
|
||||
SIM_TOP = rfnoc_block_gain_tb
|
||||
SIM_TOP = rfnoc_block_gain_tb glbl
|
||||
SIM_SRCS = \
|
||||
$(abspath $(IP_BUILD_DIR)/cmplx_mul/sim/cmplx_mul.vhd) \
|
||||
$(abspath $(IP_BUILD_DIR)/complex_multiplier/sim/complex_multiplier.vhd) \
|
||||
$(abspath rfnoc_block_gain_tb.sv) \
|
||||
$(VIVADO_PATH)/data/verilog/src/glbl.v \
|
||||
|
||||
#-------------------------------------------------
|
||||
# Bottom-of-Makefile
|
||||
|
|
|
|||
|
|
@ -17,6 +17,11 @@
|
|||
// CHDR_W : AXIS-CHDR data bus width
|
||||
// MTU : Maximum transmission unit (i.e., maximum packet size in
|
||||
// CHDR words is 2**MTU).
|
||||
// IP_OPTION : Select which IP to use for the complex multiply. Use one of
|
||||
// the following options:
|
||||
// HDL_IP = In-tree RFNoC HDL, with a DSP48E1 primitive
|
||||
// IN_TREE_IP = In-tree "complex_multiplier" (Xilinx IP)
|
||||
// OUT_OF_TREE_IP = Out-of-tree "cmplx_mul" (Xilinx IP)
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
|
@ -25,7 +30,8 @@
|
|||
module rfnoc_block_gain #(
|
||||
parameter [9:0] THIS_PORTID = 10'd0,
|
||||
parameter CHDR_W = 64,
|
||||
parameter [5:0] MTU = 10
|
||||
parameter [5:0] MTU = 10,
|
||||
parameter IP_OPTION = "HDL_IP"
|
||||
)(
|
||||
// RFNoC Framework Clocks and Resets
|
||||
input wire rfnoc_chdr_clk,
|
||||
|
|
@ -250,36 +256,104 @@ module rfnoc_block_gain #(
|
|||
wire mult_tvalid;
|
||||
wire mult_tready;
|
||||
|
||||
// Multiply complex sample by a real-valued gain. Only input the gain
|
||||
// (real_tvalid) when we have payload data to go in (cplx_tdata). That way
|
||||
// the current gain value always applies to the current sample. This assumes
|
||||
// that real_tready and cplx_tready have identical behavior.
|
||||
// Multiply each complex sample by a real-valued gain. Only input the gain
|
||||
// when we have payload data to go in (m_in_payload_tdata). That way the
|
||||
// current gain value always applies to the current sample. This assumes that
|
||||
// the tready of both inputs have identical behavior.
|
||||
//
|
||||
// Note that we receive the data with I on bits [31:16] and Q on bits [15:0],
|
||||
// but this does not matter to our multiplier.
|
||||
//
|
||||
mult_rc #(
|
||||
.WIDTH_REAL (16),
|
||||
.WIDTH_CPLX (16),
|
||||
.WIDTH_P (32),
|
||||
.DROP_TOP_P (5), // Must be 5 for a normal multiply in DSP48E1
|
||||
.LATENCY (4) // Turn on all pipeline registers in the DSP48E1
|
||||
) mult_rc_i (
|
||||
.clk (axis_data_clk),
|
||||
.reset (axis_data_rst),
|
||||
.real_tdata (reg_gain),
|
||||
.real_tlast (m_in_payload_tlast),
|
||||
.real_tvalid (m_in_payload_tvalid),
|
||||
.real_tready (),
|
||||
.cplx_tdata (m_in_payload_tdata),
|
||||
.cplx_tlast (m_in_payload_tlast),
|
||||
.cplx_tvalid (m_in_payload_tvalid),
|
||||
.cplx_tready (m_in_payload_tready),
|
||||
.p_tdata (mult_tdata),
|
||||
.p_tlast (mult_tlast),
|
||||
.p_tvalid (mult_tvalid),
|
||||
.p_tready (mult_tready)
|
||||
);
|
||||
// but the I/Q order does not matter to our complex multiplier.
|
||||
|
||||
generate
|
||||
// Use a generate statement to choose which IP to use for the multiply.
|
||||
// These all do the same thing and we only have multiple options to show
|
||||
// how you can use IP from different locations.
|
||||
|
||||
if (IP_OPTION == "HDL_IP") begin : gen_rfnoc_ip
|
||||
// Use the RFNoC mult_rc Verilog module, which uses a DSP48E1 primitive
|
||||
mult_rc #(
|
||||
.WIDTH_REAL (16),
|
||||
.WIDTH_CPLX (16),
|
||||
.WIDTH_P (32),
|
||||
.DROP_TOP_P (5), // Must be 5 for a normal multiply in DSP48E1
|
||||
.LATENCY (4) // Turn on all pipeline registers in the DSP48E1
|
||||
) mult_rc_i (
|
||||
.clk (axis_data_clk),
|
||||
.reset (axis_data_rst),
|
||||
.real_tdata (reg_gain),
|
||||
.real_tlast (m_in_payload_tlast),
|
||||
.real_tvalid (m_in_payload_tvalid),
|
||||
.real_tready (),
|
||||
.cplx_tdata (m_in_payload_tdata),
|
||||
.cplx_tlast (m_in_payload_tlast),
|
||||
.cplx_tvalid (m_in_payload_tvalid),
|
||||
.cplx_tready (m_in_payload_tready),
|
||||
.p_tdata (mult_tdata),
|
||||
.p_tlast (mult_tlast),
|
||||
.p_tvalid (mult_tvalid),
|
||||
.p_tready (mult_tready)
|
||||
);
|
||||
|
||||
end else if (IP_OPTION == "IN_TREE_IP") begin : gen_in_tree_ip
|
||||
// Use the in-tree "complex_multiplier" IP, which is a Xilinx Complex
|
||||
// Multiplier LogiCORE IP located in the UHD repository in
|
||||
// fpga/usrp3/lib/ip/.
|
||||
|
||||
// The LSB of the output is clipped in this IP, so double the gain to
|
||||
// compensate. This limits the maximum gain in this version.
|
||||
wire [15:0] gain = 2*reg_gain;
|
||||
|
||||
complex_multiplier complex_multiplier (
|
||||
.aclk (axis_data_clk),
|
||||
.aresetn (~axis_data_rst),
|
||||
.s_axis_a_tdata ({16'b0, gain}),
|
||||
.s_axis_a_tlast (m_in_payload_tlast),
|
||||
.s_axis_a_tvalid (m_in_payload_tvalid),
|
||||
.s_axis_a_tready (),
|
||||
.s_axis_b_tdata (m_in_payload_tdata),
|
||||
.s_axis_b_tlast (m_in_payload_tlast),
|
||||
.s_axis_b_tvalid (m_in_payload_tvalid),
|
||||
.s_axis_b_tready (m_in_payload_tready),
|
||||
.s_axis_ctrl_tdata (8'd0),
|
||||
.s_axis_ctrl_tvalid (1'b1),
|
||||
.s_axis_ctrl_tready (),
|
||||
.m_axis_dout_tdata (mult_tdata),
|
||||
.m_axis_dout_tlast (mult_tlast),
|
||||
.m_axis_dout_tvalid (mult_tvalid),
|
||||
.m_axis_dout_tready (mult_tready)
|
||||
);
|
||||
|
||||
end else if (IP_OPTION == "OUT_OF_TREE_IP") begin : gen_oot_ip
|
||||
// Use the out-of-tree "cmplx_mul" IP, which is a Xilinx Complex
|
||||
// Multiplier LogiCORE IP located in the IP directory of this example.
|
||||
|
||||
// This IP has a 33-bit output, but because it's AXI-Stream, each
|
||||
// component is placed in a 5-byte word. Since our gain is real only,
|
||||
// we'll never need all 33-bits.
|
||||
wire [79:0] m_axis_dout_tdata;
|
||||
|
||||
cmplx_mul cmplx_mul_i (
|
||||
.aclk (axis_data_clk),
|
||||
.aresetn (~axis_data_rst),
|
||||
.s_axis_a_tdata ({16'd0, reg_gain}),
|
||||
.s_axis_a_tlast (m_in_payload_tlast),
|
||||
.s_axis_a_tvalid (m_in_payload_tvalid),
|
||||
.s_axis_a_tready (),
|
||||
.s_axis_b_tdata (m_in_payload_tdata),
|
||||
.s_axis_b_tlast (m_in_payload_tlast),
|
||||
.s_axis_b_tvalid (m_in_payload_tvalid),
|
||||
.s_axis_b_tready (m_in_payload_tready),
|
||||
.m_axis_dout_tdata (m_axis_dout_tdata),
|
||||
.m_axis_dout_tlast (mult_tlast),
|
||||
.m_axis_dout_tvalid (mult_tvalid),
|
||||
.m_axis_dout_tready (mult_tready)
|
||||
);
|
||||
|
||||
assign mult_tdata[31: 0] = m_axis_dout_tdata[31: 0];
|
||||
assign mult_tdata[63:32] = m_axis_dout_tdata[71:40];
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Clip the results
|
||||
axi_clip_complex #(
|
||||
|
|
|
|||
Loading…
Reference in a new issue