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TEMPORARY: fpga: x400: Add YAML files for X410 FFT builds
This commit is contained in:
Wade Fife
parent
c46c3b1435
commit
4a94995c81
2 changed files with 355 additions and 0 deletions
178
fpga/usrp3/top/x400/x410_uc_200_fft_ddc_duc_rfnoc_image_core.yml
Normal file
178
fpga/usrp3/top/x400/x410_uc_200_fft_ddc_duc_rfnoc_image_core.yml
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@ -0,0 +1,178 @@
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# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: >- # Copyright information used in file headers
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Copyright 2024 Ettus Research, a National Instruments Brand
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license: >- # License information used in file headers
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SPDX-License-Identifier: LGPL-3.0-or-later
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version: '1.0' # File version
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chdr_width: 256 # Default bit width to use for CHDR buses
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device: 'x410' # USRP type
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image_core_name: 'x410_uc_200_fft_ddc_duc_routes' # Name to use for the RFNoC Image Core files
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default_target: 'X410_UC_200' # Default make target
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# A list of all stream endpoints in design
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# ----------------------------------------
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stream_endpoints:
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ep0: # Stream endpoint name
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ctrl: True # Endpoint passes control traffic
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data: True # Endpoint passes data traffic
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buff_size_bytes: 262144 # Ingress buffer size for data
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ep1:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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ep2:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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ep3:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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# A table of which crossbar routes to include
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# -------------------------------------------
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# Rows correspond to input ports and columns correspond to output ports.
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# Entering a 1 includes and a 0 removes that route from the crossbar.
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crossbar_routes:
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# eth0 eth2 eth4 ep0 ep2
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# eth1 eth3 dma ep1 ep3
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- [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth0 (NC)
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- [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth1 (NC)
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- [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth2 (NC)
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- [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth3 (NC)
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- [ 0, 0, 0, 0, 1, 0, 1, 1, 1, 1 ] # eth4 (QSFP Port 1)
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- [ 0, 0, 0, 0, 0, 1, 1, 1, 1, 1 ] # dma
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- [ 0, 0, 0, 0, 1, 1, 0, 0, 0, 0 ] # ep0 (radio0.0)
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- [ 0, 0, 0, 0, 1, 1, 0, 0, 0, 0 ] # ep1 (radio0.1)
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- [ 0, 0, 0, 0, 1, 1, 0, 0, 0, 0 ] # ep2 (radio1.0)
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- [ 0, 0, 0, 0, 1, 1, 0, 0, 0, 0 ] # ep3 (radio1.1)
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# A list of all NoC blocks in design
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# ----------------------------------
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#block_chdr_width: 64
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noc_blocks:
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ofdm_u0:
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block_desc: 'ofdm.yml'
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parameters:
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NUM_PORTS: 2
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MAX_FFT_SIZE_LOG2: 14
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MAX_CP_LEN_LOG2: 14
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ofdm_d0:
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block_desc: 'ofdm.yml'
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parameters:
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NUM_PORTS: 2
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MAX_FFT_SIZE_LOG2: 14
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MAX_CP_LEN_LOG2: 14
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duc0:
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block_desc: 'duc.yml'
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parameters:
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NUM_PORTS: 2
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ddc0:
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block_desc: 'ddc.yml'
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parameters:
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NUM_PORTS: 2
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radio0:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 2
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NIPC: RADIO_NIPC
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ctrl_clock: _device_.rfnoc_ctrl
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timebase_clock: _device_.radio
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ofdm_u1:
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block_desc: 'ofdm.yml'
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parameters:
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NUM_PORTS: 2
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MAX_FFT_SIZE_LOG2: 14
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MAX_CP_LEN_LOG2: 14
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ofdm_d1:
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block_desc: 'ofdm.yml'
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parameters:
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NUM_PORTS: 2
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MAX_FFT_SIZE_LOG2: 14
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MAX_CP_LEN_LOG2: 14
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duc1:
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block_desc: 'duc.yml'
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parameters:
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NUM_PORTS: 2
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ddc1:
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block_desc: 'ddc.yml'
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parameters:
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NUM_PORTS: 2
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radio1:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 2
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NIPC: RADIO_NIPC
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ctrl_clock: _device_.rfnoc_ctrl
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timebase_clock: _device_.radio
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# A list of all static connections in design
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# ------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect
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# - srcport = Port on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Port on the destination block to connect
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connections:
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# RF A:0 TX
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- { srcblk: ep0, srcport: out0, dstblk: ofdm_u0, dstport: in_0 }
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- { srcblk: ofdm_u0, srcport: out_0, dstblk: duc0, dstport: in_0 }
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- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
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# RF A:0 RX
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- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
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- { srcblk: ddc0, srcport: out_0, dstblk: ofdm_d0, dstport: in_0 }
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- { srcblk: ofdm_d0, srcport: out_0, dstblk: ep0, dstport: in0 }
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# RF A:1 TX
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- { srcblk: ep1, srcport: out0, dstblk: ofdm_u0, dstport: in_1 }
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- { srcblk: ofdm_u0, srcport: out_1, dstblk: duc0, dstport: in_1 }
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- { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 }
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# RF A:1 RX
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- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
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- { srcblk: ddc0, srcport: out_1, dstblk: ofdm_d0, dstport: in_1 }
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- { srcblk: ofdm_d0, srcport: out_1, dstblk: ep1, dstport: in0 }
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#
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# RF B:0 TX
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- { srcblk: ep2, srcport: out0, dstblk: ofdm_u1, dstport: in_0 }
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- { srcblk: ofdm_u1, srcport: out_0, dstblk: duc1, dstport: in_0 }
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- { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
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# RF B:0 RX
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- { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
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- { srcblk: ddc1, srcport: out_0, dstblk: ofdm_d1, dstport: in_0 }
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- { srcblk: ofdm_d1, srcport: out_0, dstblk: ep2, dstport: in0 }
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# RF B:1 TX
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- { srcblk: ep3, srcport: out0, dstblk: ofdm_u1, dstport: in_1 }
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- { srcblk: ofdm_u1, srcport: out_1, dstblk: duc1, dstport: in_1 }
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- { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 }
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# RF B:1 RX
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- { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
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- { srcblk: ddc1, srcport: out_1, dstblk: ofdm_d1, dstport: in_1 }
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- { srcblk: ofdm_d1, srcport: out_1, dstblk: ep3, dstport: in0 }
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#
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# BSP Connections
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- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
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- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
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- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
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- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
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- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
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- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
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# A list of all clock domain connections in design
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# ------------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect (Always "_device"_)
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# - srcport = Clock domain on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Clock domain on the destination block to connect
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clk_domains:
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- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
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- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
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- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
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- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
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- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
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- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
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- { srcblk: _device_, srcport: ce, dstblk: ofdm_u0, dstport: ce }
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- { srcblk: _device_, srcport: ce, dstblk: ofdm_d0, dstport: ce }
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- { srcblk: _device_, srcport: ce, dstblk: ofdm_u1, dstport: ce }
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- { srcblk: _device_, srcport: ce, dstblk: ofdm_d1, dstport: ce }
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177
fpga/usrp3/top/x400/x410_x4_200_fft_ddc_duc_rfnoc_image_core.yml
Normal file
177
fpga/usrp3/top/x400/x410_x4_200_fft_ddc_duc_rfnoc_image_core.yml
Normal file
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@ -0,0 +1,177 @@
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# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
|
||||
copyright: >- # Copyright information used in file headers
|
||||
Copyright 2024 Ettus Research, a National Instruments Brand
|
||||
license: >- # License information used in file headers
|
||||
SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
version: '1.0' # File version
|
||||
chdr_width: 64 # Default bit width to use for CHDR buses
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device: 'x410' # USRP type
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image_core_name: 'x410_x4_200_fft_ddc_duc' # Name to use for the RFNoC Image Core files
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default_target: 'X410_X4_200' # Default make target
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# A list of all stream endpoints in design
|
||||
# ----------------------------------------
|
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stream_endpoints:
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ep0: # Stream endpoint name
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ctrl: True # Endpoint passes control traffic
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data: True # Endpoint passes data traffic
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buff_size_bytes: 262144 # Ingress buffer size for data
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ep1:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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ep2:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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ep3:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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# A table of which crossbar routes to include
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# -------------------------------------------
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# Rows correspond to input ports and columns correspond to output ports.
|
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# Entering a 1 includes and a 0 removes that route from the crossbar.
|
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crossbar_routes:
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||||
# eth0 eth2 eth4 ep0 ep2
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# eth1 eth3 dma ep1 ep3
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- [ 1, 0, 0, 0, 0, 0, 1, 1, 1, 1 ] # eth0 (QSFP Port 0, Lane 0)
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- [ 0, 1, 0, 0, 0, 0, 1, 1, 1, 1 ] # eth1 (QSFP Port 0, Lane 1)
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- [ 0, 0, 1, 0, 0, 0, 1, 1, 1, 1 ] # eth2 (QSFP Port 0, Lane 2)
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- [ 0, 0, 0, 1, 0, 0, 1, 1, 1, 1 ] # eth3 (QSFP Port 0, Lane 3)
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- [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth4 (NC)
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- [ 0, 0, 0, 0, 0, 1, 1, 1, 1, 1 ] # dma
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- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0 ] # ep0 (radio0.0)
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- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0 ] # ep1 (radio0.1)
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- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0 ] # ep2 (radio1.0)
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- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0 ] # ep3 (radio1.1)
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# A list of all NoC blocks in design
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# ----------------------------------
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noc_blocks:
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ofdm_u0:
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block_desc: 'ofdm.yml'
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parameters:
|
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NUM_PORTS: 2
|
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MAX_FFT_SIZE_LOG2: 14
|
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MAX_CP_LEN_LOG2: 14
|
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ofdm_d0:
|
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block_desc: 'ofdm.yml'
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parameters:
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NUM_PORTS: 2
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MAX_FFT_SIZE_LOG2: 14
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MAX_CP_LEN_LOG2: 14
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duc0:
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block_desc: 'duc.yml'
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parameters:
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NUM_PORTS: 2
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ddc0:
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block_desc: 'ddc.yml'
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parameters:
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NUM_PORTS: 2
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radio0:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 2
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NIPC: RADIO_NIPC
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ctrl_clock: _device_.rfnoc_ctrl
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timebase_clock: _device_.radio
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ofdm_u1:
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block_desc: 'ofdm.yml'
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parameters:
|
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NUM_PORTS: 2
|
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MAX_FFT_SIZE_LOG2: 14
|
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MAX_CP_LEN_LOG2: 14
|
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ofdm_d1:
|
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block_desc: 'ofdm.yml'
|
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parameters:
|
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NUM_PORTS: 2
|
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MAX_FFT_SIZE_LOG2: 14
|
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MAX_CP_LEN_LOG2: 14
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duc1:
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block_desc: 'duc.yml'
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parameters:
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NUM_PORTS: 2
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ddc1:
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block_desc: 'ddc.yml'
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parameters:
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NUM_PORTS: 2
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radio1:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 2
|
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NIPC: RADIO_NIPC
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ctrl_clock: _device_.rfnoc_ctrl
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timebase_clock: _device_.radio
|
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|
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# A list of all static connections in design
|
||||
# ------------------------------------------
|
||||
# Format: A list of connection maps (list of key-value pairs) with the following keys
|
||||
# - srcblk = Source block to connect
|
||||
# - srcport = Port on the source block to connect
|
||||
# - dstblk = Destination block to connect
|
||||
# - dstport = Port on the destination block to connect
|
||||
connections:
|
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# RF A:0 TX
|
||||
- { srcblk: ep0, srcport: out0, dstblk: ofdm_u0, dstport: in_0 }
|
||||
- { srcblk: ofdm_u0, srcport: out_0, dstblk: duc0, dstport: in_0 }
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- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
|
||||
# RF A:0 RX
|
||||
- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
|
||||
- { srcblk: ddc0, srcport: out_0, dstblk: ofdm_d0, dstport: in_0 }
|
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- { srcblk: ofdm_d0, srcport: out_0, dstblk: ep0, dstport: in0 }
|
||||
# RF A:1 TX
|
||||
- { srcblk: ep1, srcport: out0, dstblk: ofdm_u0, dstport: in_1 }
|
||||
- { srcblk: ofdm_u0, srcport: out_1, dstblk: duc0, dstport: in_1 }
|
||||
- { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 }
|
||||
# RF A:1 RX
|
||||
- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
|
||||
- { srcblk: ddc0, srcport: out_1, dstblk: ofdm_d0, dstport: in_1 }
|
||||
- { srcblk: ofdm_d0, srcport: out_1, dstblk: ep1, dstport: in0 }
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#
|
||||
# RF B:0 TX
|
||||
- { srcblk: ep2, srcport: out0, dstblk: ofdm_u1, dstport: in_0 }
|
||||
- { srcblk: ofdm_u1, srcport: out_0, dstblk: duc1, dstport: in_0 }
|
||||
- { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
|
||||
# RF B:0 RX
|
||||
- { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
|
||||
- { srcblk: ddc1, srcport: out_0, dstblk: ofdm_d1, dstport: in_0 }
|
||||
- { srcblk: ofdm_d1, srcport: out_0, dstblk: ep2, dstport: in0 }
|
||||
# RF B:1 TX
|
||||
- { srcblk: ep3, srcport: out0, dstblk: ofdm_u1, dstport: in_1 }
|
||||
- { srcblk: ofdm_u1, srcport: out_1, dstblk: duc1, dstport: in_1 }
|
||||
- { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 }
|
||||
# RF B:1 RX
|
||||
- { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
|
||||
- { srcblk: ddc1, srcport: out_1, dstblk: ofdm_d1, dstport: in_1 }
|
||||
- { srcblk: ofdm_d1, srcport: out_1, dstblk: ep3, dstport: in0 }
|
||||
#
|
||||
# BSP Connections
|
||||
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
|
||||
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
|
||||
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
|
||||
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
||||
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
|
||||
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
|
||||
|
||||
# A list of all clock domain connections in design
|
||||
# ------------------------------------------------
|
||||
# Format: A list of connection maps (list of key-value pairs) with the following keys
|
||||
# - srcblk = Source block to connect (Always "_device"_)
|
||||
# - srcport = Clock domain on the source block to connect
|
||||
# - dstblk = Destination block to connect
|
||||
# - dstport = Clock domain on the destination block to connect
|
||||
clk_domains:
|
||||
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
|
||||
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: ofdm_u0, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: ofdm_d0, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: ofdm_u1, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: ofdm_d1, dstport: ce }
|
||||
Loading…
Reference in a new issue