mirror of
https://github.com/saymrwulf/pulp-runtime.git
synced 2026-05-19 21:32:32 +00:00
156 lines
5.4 KiB
ArmAsm
156 lines
5.4 KiB
ArmAsm
#
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# Copyright (C) 2021 ETH Zurich, University of Bologna
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#include "archi/pulp.h"
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#include "pulp.h"
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.global pos_TCLS_unload
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pos_TCLS_unload:
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# TODO: check if TCLS is supported via define
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# TODO: check if TCLS is enabled currently
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add sp, sp, -0xA0
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# zero not stored as hardwired # x0
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sw ra, 0x00(sp) # x1
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# sp stored to TCLS once complete # x2
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sw gp, 0x04(sp) # x3
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sw tp, 0x08(sp) # x4
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sw t0, 0x0C(sp) # x5
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sw t1, 0x10(sp) # x6
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sw t2, 0x14(sp) # x7
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sw x8, 0x18(sp) # fp
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sw s1, 0x1C(sp) # x9
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sw a0, 0x20(sp) # x10
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sw a1, 0x24(sp) # x11
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sw a2, 0x28(sp) # x12
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sw a3, 0x2C(sp) # x13
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sw a4, 0x30(sp) # x14
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sw a5, 0x34(sp) # x15
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sw a6, 0x38(sp) # x16
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sw a7, 0x3C(sp) # x17
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sw s2, 0x40(sp) # x18
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sw s3, 0x44(sp) # x19
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sw s4, 0x48(sp) # x20
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sw s5, 0x4C(sp) # x21
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sw s6, 0x50(sp) # x22
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sw s7, 0x54(sp) # x23
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sw s8, 0x58(sp) # x24
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sw s9, 0x5C(sp) # x25
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sw s10, 0x60(sp) # x26
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sw s11, 0x64(sp) # x27
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sw t3, 0x68(sp) # x28
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sw t4, 0x6C(sp) # x29
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sw t5, 0x70(sp) # x30
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sw t6, 0x74(sp) # x31
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csrr t1, 0x341 # mepc
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csrr t2, 0x300 # mstatus
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sw t1, 0x78(sp) # mepc
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csrr t1, 0x304 # mie
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sw t2, 0x7C(sp) # mstatus
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csrr t2, 0x305 # mtvec
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sw t1, 0x80(sp) # mie
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csrr t1, 0x340 # mscratch
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sw t2, 0x84(sp) # mtvec
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csrr t2, 0x342 # mcause
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sw t1, 0x88(sp) # mscratch
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csrr t1, 0x343 # mtval
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sw t2, 0x8C(sp) # mcause
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csrr t2, 0x7d0 # miex
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sw t1, 0x90(sp) # mtval
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csrr t1, 0x7d1 # mtvecx
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sw t2, 0x94(sp) # miex
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sw t1, 0x98(sp) # mtvecx
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csrr t0, 0xf14
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sll t0, t0, 8
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li t1, ARCHI_TCLS_ADDR
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add t0, t0, t1
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sw sp, 0x00(t0) # Store sp to TCLS sp reg -> subsequent mismatches will trigger restart of resynchronization
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nop
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nop
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nop
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.global pos_TCLS_reload
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pos_TCLS_reload:
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csrr t0, 0xf14
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sll t0, t0, 8
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li t1, ARCHI_TCLS_ADDR
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add t0, t0, t1
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lw sp, 0x00(t0)
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lw t1, 0x78(sp) # mepc
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lw t2, 0x7C(sp) # mstatus
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csrw 0x341, t1 # mepc
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lw t1, 0x80(sp) # mie
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csrw 0x300, t2 # mstatus
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lw t2, 0x84(sp) # mtvec
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csrw 0x304, t1 # mie
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lw t1, 0x88(sp) # mscratch
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csrw 0x305, t2 # mtvec
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lw t2, 0x8C(sp) # mcause
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csrw 0x340, t1 # mscratch
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lw t1, 0x90(sp) # mtval
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csrw 0x342, t2 # mcause
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lw t2, 0x94(sp) # miex
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csrw 0x343, t1 # mtval
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lw t1, 0x98(sp) # mtvecx
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csrw 0x7d0, t2 # miex
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csrw 0x7d1, t1 # mtvecx
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# zero not loaded as hardwired # x0
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lw ra, 0x00(sp) # x1
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# sp loaded from TCLS above # x2
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lw gp, 0x04(sp) # x3
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lw tp, 0x08(sp) # x4
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# t0 loaded below, as this reg stores pointer to TCLS unit
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# lw t0, 0x0C(sp) # x5
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lw t1, 0x10(sp) # x6
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lw t2, 0x14(sp) # x7
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lw x8, 0x18(sp) # fp
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lw s1, 0x1C(sp) # x9
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lw a0, 0x20(sp) # x10
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lw a1, 0x24(sp) # x11
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lw a2, 0x28(sp) # x12
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lw a3, 0x2C(sp) # x13
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lw a4, 0x30(sp) # x14
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lw a5, 0x34(sp) # x15
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lw a6, 0x38(sp) # x16
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lw a7, 0x3C(sp) # x17
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lw s2, 0x40(sp) # x18
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lw s3, 0x44(sp) # x19
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lw s4, 0x48(sp) # x20
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lw s5, 0x4C(sp) # x21
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lw s6, 0x50(sp) # x22
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lw s7, 0x54(sp) # x23
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lw s8, 0x58(sp) # x24
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lw s9, 0x5C(sp) # x25
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lw s10, 0x60(sp) # x26
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lw s11, 0x64(sp) # x27
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lw t3, 0x68(sp) # x28
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lw t4, 0x6C(sp) # x29
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lw t5, 0x70(sp) # x30
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lw t6, 0x74(sp) # x31
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sw zero, 0x00(t0) # Clear TCLS sp reg -> subsequent mismatches will trigger unload and reload
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lw t0, 0x0C(sp) # x5
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add sp, sp, 0xA0
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mret
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