mirror of
https://github.com/saymrwulf/pulp-runtime.git
synced 2026-06-22 02:30:34 +00:00
196 lines
No EOL
8.2 KiB
C
196 lines
No EOL
8.2 KiB
C
/*
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* Copyright (C) 2018 ETH Zurich and University of Bologna
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __ARCHI_UDMA_UDMA_SPIM_V2_H__
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#define __ARCHI_UDMA_UDMA_SPIM_V2_H__
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#define ARCHI_SPIM_CMD_OFFSET 0x20
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// SPI commands IDS definition
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#define SPI_CMD_CFG_ID 0
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#define SPI_CMD_SOT_ID 1
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#define SPI_CMD_SEND_CMD_ID 2
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#define SPI_CMD_SEND_BITS_ID 2
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#define SPI_CMD_SEND_ADDR_ID 3
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#define SPI_CMD_DUMMY_ID 4
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#define SPI_CMD_WAIT_ID 5
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#define SPI_CMD_TX_DATA_ID 6
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#define SPI_CMD_RX_DATA_ID 7
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#define SPI_CMD_RPT_ID 8
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#define SPI_CMD_EOT_ID 9
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#define SPI_CMD_RPT_END_ID 10
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#define SPI_CMD_RX_CHECK_ID 11
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#define SPI_CMD_FUL_ID 12
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// SPI command fields offset, mask, value definition
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// SPI commands fields offsets
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#define SPI_CMD_ID_OFFSET 28
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// COMMON definitions
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#define SPI_CMD_QPI_ENA 1
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#define SPI_CMD_QPI_DIS 0
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#define SPI_CMD_LSB_FIRST 1
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#define SPI_CMD_MSB_FIRST 0
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#define SPI_CMD_4_WORD_PER_TRANSF 2
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#define SPI_CMD_2_WORD_PER_TRANSF 1
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#define SPI_CMD_1_WORD_PER_TRANSF 0
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#define SPI_CMD_DATA_WITDH(val) (val)
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#define SPI_CMD_CMD_SIZE(val) (val)
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// CFG
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#define SPI_CMD_CFG_CLK_DIV_OFFSET 0
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#define SPI_CMD_CFG_CLK_DIV_WIDTH 8
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#define SPI_CMD_CFG_CPHA_OFFSET 8
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#define SPI_CMD_CFG_CPOL_OFFSET 9
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#define SPI_CMD_CFG_CLKDIV(val) (val)
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#define SPI_CMD_CFG_CPOL_POS 1
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#define SPI_CMD_CFG_CPOL_NEG 0
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#define SPI_CMD_CFG_CPHA_STD 1
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#define SPI_CMD_CFG_CPHA_OPP 0
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// SOT
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#define SPI_CMD_SOT_CS_OFFSET 0
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#define SPI_CMD_SOT_CS_WIDTH 2
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#define SPI_CMD_SOT_CS0 0
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#define SPI_CMD_SOT_CS1 1
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#define SPI_CMD_SOT_CS2 2
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#define SPI_CMD_SOT_CS3 3
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// SEND_CMD
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#define SPI_CMD_SEND_CMD_CMD_OFFSET 0
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#define SPI_CMD_SEND_CMD_CMD_WIDTH 16
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#define SPI_CMD_SEND_CMD_SIZE_OFFSET 16
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#define SPI_CMD_SEND_CMD_SIZE_WIDTH 4
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#define SPI_CMD_SEND_CMD_QPI_OFFSET 27
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// SEND_CMD
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#define SPI_CMD_SEND_BITS_BITS_OFFSET 0
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#define SPI_CMD_SEND_BITS_BITS_WIDTH 16
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#define SPI_CMD_SEND_BITS_SIZE_OFFSET 16
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#define SPI_CMD_SEND_BITS_SIZE_WIDTH 4
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#define SPI_CMD_SEND_BITS_QPI_OFFSET 27
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// SEND_ADDR
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#define SPI_CMD_SEND_ADDR_SIZE_OFFSET 16
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#define SPI_CMD_SEND_ADDR_SIZE_WIDTH 5
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#define SPI_CMD_SEND_ADDR_QPI_OFFSET 27
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//#define SPI_CMD_SEND_ADDR_VALUE(value) ((((value) & 0xff000000) >> 24) | (((value) & 0xff0000) >> 8) | (((value) & 0xff00) << 8) | (((value) & 0xff) << 24))
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#define SPI_CMD_SEND_ADDR_VALUE(value) (value)
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// SEND_DUMMY
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#define SPI_CMD_DUMMY_CYCLE_OFFSET 16
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#define SPI_CMD_DUMMY_CYCLE_WIDTH 5
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// TX_DATA
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#define SPI_CMD_TX_DATA_SIZE_OFFSET 0
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#define SPI_CMD_TX_DATA_SIZE_WIDTH 16
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#define SPI_CMD_TX_DATA_QPI_OFFSET 27
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#define SPI_CMD_TX_DATA_WORDTRANS_OFFSET 21
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#define SPI_CMD_TX_DATA_WORDTRANS_WIDTH 2
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#define SPI_CMD_TX_DATA_LSBFIRST_OFFSET 26
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#define SPI_CMD_TX_DATA_BITSWORD_OFFSET 16
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#define SPI_CMD_TX_DATA_BITSWORD_WIDTH 5
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// RX_DATA
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#define SPI_CMD_RX_DATA_SIZE_OFFSET 0
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#define SPI_CMD_RX_DATA_SIZE_WIDTH 16
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#define SPI_CMD_RX_DATA_QPI_OFFSET 27
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#define SPI_CMD_RX_DATA_WORDTRANS_OFFSET 21
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#define SPI_CMD_RX_DATA_WORDTRANS_WIDTH 2
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#define SPI_CMD_RX_DATA_LSBFIRST_OFFSET 26
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#define SPI_CMD_RX_DATA_BITSWORD_OFFSET 16
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#define SPI_CMD_RX_DATA_BITSWORD_WIDTH 5
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// RPT
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#define SPI_CMD_RPT_NB_OFFSET 0
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#define SPI_CMD_RPT_NB_WIDTH 16
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// EOT
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#define SPI_CMD_EOT_GEN_EVT_OFFSET 0
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#define SPI_CMD_EOT_CS_KEEP_OFFSET 1
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#define SPI_CMD_EOT_EVENT_ENA 1
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#define SPI_CMD_EOT_EVENT_DIS 0
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// WAIT
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#define SPI_CMD_WAIT_EVENT_OFFSET 0
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#define SPI_CMD_WAIT_EVENT_WIDTH 2
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// RX_CHECK
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#define SPI_CMD_RX_CHECK_VALUE_OFFSET 0
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#define SPI_CMD_RX_CHECK_VALUE_WIDTH 16
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#define SPI_CMD_RX_CHECK_SIZE_OFFSET 16
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#define SPI_CMD_RX_CHECK_SIZE_WIDTH 4
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#define SPI_CMD_RX_CHECK_MODE_OFFSET 24
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#define SPI_CMD_RX_CHECK_MODE_WIDTH 2
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#define SPI_CMD_RX_CHECK_BYTE_ALIGN_OFFSET 26
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#define SPI_CMD_RX_CHECK_QPI_OFFSET 27
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#define SPI_CMD_RX_CHECK_MODE_MATCH 0
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#define SPI_CMD_RX_CHECK_MODE_ONES 1
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#define SPI_CMD_RX_CHECK_MODE_ZEROS 2
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#define SPI_CMD_RX_CHECK_MODE_MASK 3
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// FULL DUPLEX
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#define SPI_CMD_FUL_SIZE_OFFSET 0
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#define SPI_CMD_FUL_SIZE_WIDTH 16
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#define SPI_CMD_FUL_WORDTRANS_OFFSET 21
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#define SPI_CMD_FUL_WORDTRANS_WIDTH 2
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#define SPI_CMD_FUL_LSBFIRST_OFFSET 26
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#define SPI_CMD_FUL_BITSWORD_OFFSET 16
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#define SPI_CMD_FUL_BITSWORD_WIDTH 5
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#define SPI_CMD_SETUP_UC_TXRXEN_OFFSET 27
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#define SPI_CMD_SETUP_UC_DS_OFFSET 25
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// SPI CMD encoding
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#define SPI_CMD_CFG(clockDiv,cpol,cpha) ((SPI_CMD_CFG_ID<<SPI_CMD_ID_OFFSET) | ((cpol)<<SPI_CMD_CFG_CPOL_OFFSET) | ((cpha)<<SPI_CMD_CFG_CPHA_OFFSET) | ((clockDiv)<<SPI_CMD_CFG_CLK_DIV_OFFSET))
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#define SPI_CMD_SOT(cs) ((SPI_CMD_SOT_ID << SPI_CMD_ID_OFFSET) | ((cs) << SPI_CMD_SOT_CS_OFFSET))
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#define SPI_CMD_SEND_CMD(cmd,bits,qpi) ((SPI_CMD_SEND_CMD_ID<<SPI_CMD_ID_OFFSET) | ((qpi)<<SPI_CMD_SEND_CMD_QPI_OFFSET) | (((bits)-1)<<SPI_CMD_SEND_CMD_SIZE_OFFSET) | (cmd&0xFFFF) )
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#define SPI_CMD_SEND_BITS(data,bits,qpi) ((SPI_CMD_SEND_CMD_ID<<SPI_CMD_ID_OFFSET) | ((qpi)<<SPI_CMD_SEND_CMD_QPI_OFFSET) | (((bits)-1)<<SPI_CMD_SEND_CMD_SIZE_OFFSET) | (data&0xFFFF) )
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#define SPI_CMD_DUMMY(cycles) ((SPI_CMD_DUMMY_ID<<SPI_CMD_ID_OFFSET) | (((cycles)-1)<<SPI_CMD_DUMMY_CYCLE_OFFSET))
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#define SPI_CMD_SETUP_UCA(txrxen,ds,addr) ((SPI_CMD_SETUP_UCA_ID<<SPI_CMD_ID_OFFSET) | ((txrxen)<<SPI_CMD_SETUP_UC_TXRXEN_OFFSET) | ((int)addr & 0xFFFFF))
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#define SPI_CMD_SETUP_UCS(txrxen,ds,size) ((SPI_CMD_SETUP_UCS_ID<<SPI_CMD_ID_OFFSET) | ((txrxen)<<SPI_CMD_SETUP_UC_TXRXEN_OFFSET) | ((ds)<<SPI_CMD_SETUP_UC_DS_OFFSET) | (size & 0xFFFF))
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#define SPI_CMD_TX_DATA(words,wordstrans,bitsword,qpi,lsbfirst) ((SPI_CMD_TX_DATA_ID<<SPI_CMD_ID_OFFSET) | ((qpi)<<SPI_CMD_TX_DATA_QPI_OFFSET) | ((wordstrans)<<SPI_CMD_TX_DATA_WORDTRANS_OFFSET) | ((bitsword-1)<<SPI_CMD_TX_DATA_BITSWORD_OFFSET) | (((words)-1) << SPI_CMD_TX_DATA_SIZE_OFFSET) | ((lsbfirst)<<SPI_CMD_TX_DATA_LSBFIRST_OFFSET))
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#define SPI_CMD_RX_DATA(words,wordstrans,bitsword,qpi,lsbfirst) ((SPI_CMD_RX_DATA_ID<<SPI_CMD_ID_OFFSET) | ((qpi)<<SPI_CMD_RX_DATA_QPI_OFFSET) | ((wordstrans)<<SPI_CMD_RX_DATA_WORDTRANS_OFFSET) | ((bitsword-1)<<SPI_CMD_RX_DATA_BITSWORD_OFFSET) | (((words)-1) << SPI_CMD_RX_DATA_SIZE_OFFSET) | ((lsbfirst)<<SPI_CMD_RX_DATA_LSBFIRST_OFFSET))
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#define SPI_CMD_RPT(iter) ((SPI_CMD_RPT_ID<<SPI_CMD_ID_OFFSET) | ((iter)<<SPI_CMD_RPT_NB_OFFSET))
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#define SPI_CMD_EOT(evt,cs_keep) ((SPI_CMD_EOT_ID<<28) | ((evt)<<SPI_CMD_EOT_GEN_EVT_OFFSET) | ((cs_keep)<<SPI_CMD_EOT_CS_KEEP_OFFSET))
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#define SPI_CMD_RX_CHECK(mode,bits,value,qpi,byte_align) \
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((SPI_CMD_RX_CHECK_ID<<SPI_CMD_ID_OFFSET) | \
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((value) << SPI_CMD_RX_CHECK_VALUE_OFFSET) | \
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((mode) << SPI_CMD_RX_CHECK_MODE_OFFSET) | \
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(((bits)-1) << SPI_CMD_RX_CHECK_SIZE_OFFSET) | \
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((byte_align)<<SPI_CMD_RX_CHECK_BYTE_ALIGN_OFFSET) | \
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((qpi)<<SPI_CMD_RX_CHECK_QPI_OFFSET))
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#define SPI_CMD_WAIT(event) ((SPI_CMD_WAIT_ID<<SPI_CMD_ID_OFFSET) | ((event) << SPI_CMD_WAIT_EVENT_OFFSET))
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#define SPI_CMD_RPT_END() ((SPI_CMD_RPT_END_ID<<SPI_CMD_ID_OFFSET))
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#define SPI_CMD_FUL(words,wordstrans,bitsword,lsbfirst) ((SPI_CMD_FUL_ID<<SPI_CMD_ID_OFFSET) | ((wordstrans)<<SPI_CMD_FUL_WORDTRANS_OFFSET) | ((bitsword-1)<<SPI_CMD_FUL_BITSWORD_OFFSET) | (((words)-1) << SPI_CMD_FUL_SIZE_OFFSET) | ((lsbfirst)<<SPI_CMD_FUL_LSBFIRST_OFFSET))
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#endif |