mirror of
https://github.com/saymrwulf/pulp-runtime.git
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192 lines
6 KiB
C
192 lines
6 KiB
C
/*
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* Copyright (C) 2023 ETH Zurich and University of Bologna
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __ARCHI_HMR_HMR_V1_H__
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#define __ARCHI_HMR_HMR_V1_H__
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#define HMR_IN_INTERLEAVED 1
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#define HMR_TOP_OFFSET 0x000
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#define HMR_CORE_OFFSET 0x100
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#define HMR_DMR_OFFSET 0x200
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#define HMR_TMR_OFFSET 0x300
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#define HMR_CORE_INCREMENT 0x010
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#define HMR_CORE_SLL 0x004
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#define HMR_DMR_INCREMENT 0x010
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#define HMR_DMR_SLL 0x004
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#define HMR_TMR_INCREMENT 0x010
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#define HMR_TMR_SLL 0x004
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// Generated register defines for HMR_registers
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#ifndef _HMR_REGISTERS_REG_DEFS_
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#define _HMR_REGISTERS_REG_DEFS_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define HMR_REGISTERS_PARAM_NUM_CORES 12
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#define HMR_REGISTERS_PARAM_NUM_D_M_R_GROUPS 6
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#define HMR_REGISTERS_PARAM_NUM_T_M_R_GROUPS 4
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// Register width
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#define HMR_REGISTERS_PARAM_REG_WIDTH 32
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// Available Configurations from implemented hardware.
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#define HMR_REGISTERS_AVAIL_CONFIG_REG_OFFSET 0x0
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#define HMR_REGISTERS_AVAIL_CONFIG_INDEPENDENT_BIT 0
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#define HMR_REGISTERS_AVAIL_CONFIG_DUAL_BIT 1
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#define HMR_REGISTERS_AVAIL_CONFIG_TRIPLE_BIT 2
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#define HMR_REGISTERS_AVAIL_CONFIG_RAPID_RECOVERY_BIT 8
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// Enabled cores, based on the configuration. Can be used for barriers.
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#define HMR_REGISTERS_CORES_EN_REG_OFFSET 0x4
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#define HMR_REGISTERS_CORES_EN_CORES_EN_MASK 0xfff
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#define HMR_REGISTERS_CORES_EN_CORES_EN_OFFSET 0
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#define HMR_REGISTERS_CORES_EN_CORES_EN_FIELD \
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((bitfield_field32_t) { .mask = HMR_REGISTERS_CORES_EN_CORES_EN_MASK, .index = HMR_REGISTERS_CORES_EN_CORES_EN_OFFSET })
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// DMR configuration enable, on bit per DMR group.
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#define HMR_REGISTERS_DMR_ENABLE_REG_OFFSET 0x8
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#define HMR_REGISTERS_DMR_ENABLE_DMR_ENABLE_MASK 0x3f
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#define HMR_REGISTERS_DMR_ENABLE_DMR_ENABLE_OFFSET 0
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#define HMR_REGISTERS_DMR_ENABLE_DMR_ENABLE_FIELD \
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((bitfield_field32_t) { .mask = HMR_REGISTERS_DMR_ENABLE_DMR_ENABLE_MASK, .index = HMR_REGISTERS_DMR_ENABLE_DMR_ENABLE_OFFSET })
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// TMR configuration enable, one bit per TMR group.
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#define HMR_REGISTERS_TMR_ENABLE_REG_OFFSET 0xc
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#define HMR_REGISTERS_TMR_ENABLE_TMR_ENABLE_MASK 0xf
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#define HMR_REGISTERS_TMR_ENABLE_TMR_ENABLE_OFFSET 0
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#define HMR_REGISTERS_TMR_ENABLE_TMR_ENABLE_FIELD \
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((bitfield_field32_t) { .mask = HMR_REGISTERS_TMR_ENABLE_TMR_ENABLE_MASK, .index = HMR_REGISTERS_TMR_ENABLE_TMR_ENABLE_OFFSET })
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// DMR configuration bits.
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#define HMR_REGISTERS_DMR_CONFIG_REG_OFFSET 0x10
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#define HMR_REGISTERS_DMR_CONFIG_RAPID_RECOVERY_BIT 0
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#define HMR_REGISTERS_DMR_CONFIG_FORCE_RECOVERY_BIT 1
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#define HMR_REGISTERS_DMR_CONFIG_SETBACK_BIT 2
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#define HMR_REGISTERS_DMR_CONFIG_SYNCH_REQ_BIT 3
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// TMR configuration bits.
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#define HMR_REGISTERS_TMR_CONFIG_REG_OFFSET 0x14
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#define HMR_REGISTERS_TMR_CONFIG_DELAY_RESYNCH_BIT 0
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#define HMR_REGISTERS_TMR_CONFIG_SETBACK_BIT 1
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#define HMR_REGISTERS_TMR_CONFIG_RELOAD_SETBACK_BIT 2
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#define HMR_REGISTERS_TMR_CONFIG_RAPID_RECOVERY_BIT 3
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#define HMR_REGISTERS_TMR_CONFIG_FORCE_RESYNCH_BIT 4
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#define HMR_REGISTERS_TMR_CONFIG_SYNCH_REQ_BIT 5
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // _HMR_REGISTERS_REG_DEFS_
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// End generated register defines for HMR_registers
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// Generated register defines for HMR_core_regs
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#ifndef _HMR_CORE_REGS_REG_DEFS_
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#define _HMR_CORE_REGS_REG_DEFS_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Register width
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#define HMR_CORE_REGS_PARAM_REG_WIDTH 32
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// Value to determine wich redundancy mode the core with that ID is in.
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#define HMR_CORE_REGS_CURRENT_MODE_REG_OFFSET 0x0
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#define HMR_CORE_REGS_CURRENT_MODE_INDEPENDENT_BIT 0
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#define HMR_CORE_REGS_CURRENT_MODE_DUAL_BIT 1
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#define HMR_CORE_REGS_CURRENT_MODE_TRIPLE_BIT 2
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// Mismatches of the core
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#define HMR_CORE_REGS_MISMATCHES_REG_OFFSET 0x4
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// Stack Pointer storage register
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#define HMR_CORE_REGS_SP_STORE_REG_OFFSET 0x8
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // _HMR_CORE_REGS_REG_DEFS_
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// End generated register defines for HMR_core_regs
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// Generated register defines for HMR_dmr_regs
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#ifndef _HMR_DMR_REGS_REG_DEFS_
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#define _HMR_DMR_REGS_REG_DEFS_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Register width
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#define HMR_DMR_REGS_PARAM_REG_WIDTH 32
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// DMR configuration enable.
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#define HMR_DMR_REGS_DMR_ENABLE_REG_OFFSET 0x0
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#define HMR_DMR_REGS_DMR_ENABLE_DMR_ENABLE_BIT 0
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// DMR configuration bits.
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#define HMR_DMR_REGS_DMR_CONFIG_REG_OFFSET 0x4
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#define HMR_DMR_REGS_DMR_CONFIG_RAPID_RECOVERY_BIT 0
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#define HMR_DMR_REGS_DMR_CONFIG_FORCE_RECOVERY_BIT 1
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#define HMR_DMR_REGS_DMR_CONFIG_SETBACK_BIT 2
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#define HMR_DMR_REGS_DMR_CONFIG_SYNCH_REQ_BIT 3
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// Address for the last checkpoint.
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#define HMR_DMR_REGS_CHECKPOINT_ADDR_REG_OFFSET 0x8
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // _HMR_DMR_REGS_REG_DEFS_
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// End generated register defines for HMR_dmr_regs
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// Generated register defines for HMR_tmr_regs
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#ifndef _HMR_TMR_REGS_REG_DEFS_
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#define _HMR_TMR_REGS_REG_DEFS_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Register width
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#define HMR_TMR_REGS_PARAM_REG_WIDTH 32
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// TMR configuration enable.
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#define HMR_TMR_REGS_TMR_ENABLE_REG_OFFSET 0x0
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#define HMR_TMR_REGS_TMR_ENABLE_TMR_ENABLE_BIT 0
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// TMR configuration bits.
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#define HMR_TMR_REGS_TMR_CONFIG_REG_OFFSET 0x4
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#define HMR_TMR_REGS_TMR_CONFIG_DELAY_RESYNCH_BIT 0
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#define HMR_TMR_REGS_TMR_CONFIG_SETBACK_BIT 1
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#define HMR_TMR_REGS_TMR_CONFIG_RELOAD_SETBACK_BIT 2
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#define HMR_TMR_REGS_TMR_CONFIG_RAPID_RECOVERY_BIT 3
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#define HMR_TMR_REGS_TMR_CONFIG_FORCE_RESYNCH_BIT 4
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#define HMR_TMR_REGS_TMR_CONFIG_SYNCH_REQ_BIT 5
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // _HMR_TMR_REGS_REG_DEFS_
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// End generated register defines for HMR_tmr_regs
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#endif // __ARCHI_HMR_HMR_V1_H__
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