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96 lines
5 KiB
C
96 lines
5 KiB
C
/*
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* Copyright (C) 2020 ETH Zurich and University of Bologna
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _ARCHI_IBEX_MHPM_H
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#define _ARCHI_IBEX_MHPM_H
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/*
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* Bit definitions for Performance counters mode registers
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*
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*/
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#define IBEX_MHPMCOUNTER_BASE 0xB00
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// Currently the additional register for more perf. counting is not yet implemented
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// ibex performance counters
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#define IBEX_NumCycles 0 /* Number of cycles */
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#define IBEX_NumInstrRet 2 /* Number of instructions retired */
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#define IBEX_NumCyclesLSU 3 /* Number of cycles waiting for data memory */
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#define IBEX_NumCyclesIF 4 /* Cycles waiting for instruction fetches, i.e., number of instructions wasted due to non-ideal caching */
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#define IBEX_NumLoads 5 /* Number of data memory loads. Misaligned accesses are counted as two accesses */
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#define IBEX_NumStores 6 /* Number of data memory stores. Misaligned accesses are counted as two accesses */
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#define IBEX_NumJumps 7 /* Number of unconditional jumps (j, jal, jr, jalr) */
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#define IBEX_NumBranches 8 /* Number of branches (conditional) */
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#define IBEX_NumBranchesTaken 9 /* Number of taken branches (conditional) */
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#define IBEX_NumInstrRetC 10 /* Number of compressed instructions retired */
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#define IBEX_NumCyclesMulWait 11 /* Cycles waiting for multiply to complete */
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#define IBEX_NumCyclesDivWait 12 /* Cycles waiting for divide to complete */
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// riscv map for ibex counters
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#define CSR_PCER_CYCLES IBEX_NumCycles /* Count the number of cycles the core was running */
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#define CSR_PCER_INSTR IBEX_NumInstrRet /* Count the number of instructions executed */
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#define CSR_PCER_LD_STALL IBEX_NumCyclesLSU /* Number of load use hazards */
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#define CSR_PCER_IMISS IBEX_NumCyclesIF /* Cycles waiting for instruction fetches. i.e. the number of instructions wasted due to non-ideal caches */
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#define CSR_PCER_LD IBEX_NumLoads /* Number of memory loads executed. Misaligned accesses are counted twice */
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#define CSR_PCER_ST IBEX_NumStores /* Number of memory stores executed. Misaligned accesses are counted twice */
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#define CSR_PCER_JUMP IBEX_NumJumps /* Number of jump instructions seen, i.e. j, jr, jal, jalr */
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#define CSR_PCER_BRANCH IBEX_NumBranches /* Number of branch instructions seen, i.e. bf, bnf */
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#define CSR_PCER_TAKEN_BRANCH IBEX_NumBranchesTaken /* Number of taken branch instructions seen, i.e. bf, bnf */
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#define CSR_PCER_RVC IBEX_NumInstrRetC /* Number of compressed instructions */
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// Not implemented in ibex
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// #define CSR_PCER_ELW 0 /* Cycles wasted due to ELW instruction */
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// #define CSR_PCER_JMP_STALL 0 /* Number of jump register hazards */
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// External perf counters
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#define IBEX_External_BASE 13
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#define CSR_PCER_LD_EXT 13 /* Number of memory loads to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */
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#define CSR_PCER_ST_EXT 14 /* Number of memory stores to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */
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#define CSR_PCER_LD_EXT_CYC 15 /* Cycles used for memory loads to EXT. Every non-TCDM access is considered external */
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#define CSR_PCER_ST_EXT_CYC 16 /* Cycles used for memory stores to EXT. Every non-TCDM access is considered external */
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#define CSR_PCER_TCDM_CONT 17 /* Cycles wasted due to TCDM/log-interconnect contention */
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#define CSR_PCER_NB_EVENTS 16
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#define CSR_PCER_TOP_EVENT 17
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#define CSR_PCER_NB_INTERNAL_EVENTS 11
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#define CSR_PCER_TOP_INTERNAL_EVENTS 12
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#define CSR_NB_PCCR 32
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// Gives from the event ID, the HW mask that can be stored (with an OR with other events mask) to the PCER
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#define CSR_PCER_EVENT_MASK(eventId) (1<<(eventId))
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#define CSR_PCER_ALL_EVENTS_MASK 0xffffffff
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#define CSR_PCER_NAME(id) \
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( id == IBEX_NumCycles ? "Cycles" : \
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id == IBEX_NumInstrRet ? "Instructions" : \
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id == IBEX_NumCyclesLSU ? "LD_Stall" : \
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id == IBEX_NumCyclesIF ? "IMISS" : \
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id == IBEX_NumLoads ? "LD" : \
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id == IBEX_NumStores ? "ST" : \
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id == IBEX_NumJumps ? "JUMP" : \
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id == IBEX_NumBranches ? "BRANCH" : \
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id == IBEX_NumBranchesTaken ? "TAKEN_BRANCH" : \
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id == IBEX_NumInstrRetC ? "RVC" : \
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id == 16 ? "LD_EXT" : \
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id == 17 ? "ST_EXT" : \
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id == 18 ? "LD_EXT_CYC" : \
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id == 19 ? "ST_EXT_CYC" : \
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id == 20 ? "TCDM_CONT" : \
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"NA")
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#endif
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