mirror of
https://github.com/saymrwulf/pulp-runtime.git
synced 2026-05-14 20:48:09 +00:00
262 lines
6.6 KiB
C
262 lines
6.6 KiB
C
/*
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* Copyright (C) 2018 ETH Zurich, University of Bologna
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __ARCHI_CHIPS_KAIROS_PROPERTIES_H__
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#define __ARCHI_CHIPS_KAIROS_PROPERTIES_H__
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/*
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* FPGA
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*/
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/*
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* MEMORIES
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*/
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#define ARCHI_HAS_L2 1
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#define ARCHI_HAS_L2_MULTI 1
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#define ARCHI_L2_PRIV0_ADDR 0x1c000000
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#define ARCHI_L2_PRIV0_SIZE 0x00008000
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#define ARCHI_L2_PRIV1_ADDR 0x1c008000
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#define ARCHI_L2_PRIV1_SIZE 0x00008000
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#define ARCHI_L2_SHARED_ADDR 0x1c010000
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#define ARCHI_L2_SHARED_SIZE 0x00070000
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/*
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* MEMORY ALIAS
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*/
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#define ARCHI_HAS_L2_ALIAS 1
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/*
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* IP VERSIONS
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*/
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#define UDMA_VERSION 3
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#define PERIPH_VERSION 2
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#define TIMER_VERSION 2
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#define SOC_EU_VERSION 2
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#define APB_SOC_VERSION 3
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#define STDOUT_VERSION 2
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#define GPIO_VERSION 2
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#define EU_VERSION 3
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#define ITC_VERSION 1
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#define FLL_VERSION 1
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#define RISCV_VERSION 4
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#define PADS_VERSION 2
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/*
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* HWS
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*/
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#define ARCHI_EU_NB_HW_MUTEX 1
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/*
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* FC
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*/
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#define ARCHI_FC_CID 31
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#define ARCHI_HAS_FC_ITC 1
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#define ARCHI_HAS_FC 1
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#define ARCHI_CORE_HAS_1_10 1
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/*
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* CLOCKS
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*/
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#define ARCHI_REF_CLOCK_LOG2 15
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#define ARCHI_REF_CLOCK (1<<ARCHI_REF_CLOCK_LOG2)
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/*
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* UDMA
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*/
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#define ARCHI_UDMA_HAS_SPIM 1
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#define ARCHI_UDMA_HAS_UART 1
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#define ARCHI_UDMA_HAS_SDIO 0
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#define ARCHI_UDMA_HAS_I2C 1
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#define ARCHI_UDMA_HAS_I2S 0
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#define ARCHI_UDMA_HAS_CAM 0
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#define ARCHI_UDMA_HAS_TRACER 0
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#define ARCHI_UDMA_HAS_FILTER 0
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#define ARCHI_UDMA_NB_SPIM 8
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#define ARCHI_UDMA_NB_UART 1
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#define ARCHI_UDMA_NB_SDIO 0
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#define ARCHI_UDMA_NB_I2C 12
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#define ARCHI_UDMA_NB_I2S 0
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#define ARCHI_UDMA_NB_CAM 0
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#define ARCHI_UDMA_NB_TRACER 0
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#define ARCHI_UDMA_NB_FILTER 1
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#define ARCHI_UDMA_UART_ID(id) 0
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#define ARCHI_UDMA_SPIM_ID(id) (1 + (id))
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#define ARCHI_UDMA_I2C_ID(id) (9 + (id))
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#define ARCHI_UDMA_FILTER_ID(id) (21 + (id))
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#define ARCHI_NB_PERIPH 22
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#define ARCHI_UDMA_NB_I2C_MAX 12
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#define ARCHI_UDMA_NB_SPIM_MAX 8
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/*
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* FLLS
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*/
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#define ARCHI_NB_FLL 2
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/*
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* SOC EVENTS
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*/
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#define ARCHI_SOC_EVENT_PERIPH_EVT_NB 160
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#define ARCHI_SOC_EVENT_SW_NB (8)
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#define ARCHI_SOC_EVENT_NB_TOTAL 256
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#define ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT_LOG2 2
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#define ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT (1<<ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT_LOG2)
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#define ARCHI_SOC_EVENT_UDMA_FIRST_EVT 0
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#define ARCHI_SOC_EVENT_UDMA_NB_EVT (ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT * ARCHI_NB_PERIPH_MAX)
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#define ARCHI_SOC_EVENT_UDMA_NB_TGEN_EVT 6
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#define ARCHI_SOC_EVENT_UDMA_NB_EVT_MAX 32*4
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#define ARCHI_NB_PERIPH_MAX ((ARCHI_SOC_EVENT_UDMA_NB_EVT_MAX-ARCHI_UDMA_NB_SPIM_MAX-ARCHI_UDMA_NB_I2C_MAX)>>2)
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#define ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(x) ((x)*ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT)
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#define ARCHI_SOC_EVENT_UART0_RX 0
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#define ARCHI_SOC_EVENT_UART0_TX 1
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#define ARCHI_SOC_EVENT_UART0_EOT 2
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#define ARCHI_SOC_EVENT_UART0_RX_DATA 3
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#define ARCHI_SOC_EVENT_SPIM_RX (id) (4 + (id) * 4)
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#define ARCHI_SOC_EVENT_SPIM_TX (id) (5 + (id) * 4)
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#define ARCHI_SOC_EVENT_SPIM_CMD(id) (6 + (id) * 4)
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#define ARCHI_SOC_EVENT_SPIM_EOT(id) (7 + (id) * 4)
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#define ARCHI_SOC_EVENT_SPIM_REQ(id) (ARCHI_SOC_EVENT_UDMA_NB_EVT + (id))
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#define ARCHI_SOC_EVENT_I2C0_RX 8
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#define ARCHI_SOC_EVENT_I2C0_TX 9
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#define ARCHI_SOC_EVENT_I2C1_RX 12
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#define ARCHI_SOC_EVENT_I2C1_TX 13
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#define ARCHI_SOC_EVENT_SDIO0_RX 16
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#define ARCHI_SOC_EVENT_SDIO0_TX 17
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#define ARCHI_SOC_EVENT_I2S0_RX 20
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#define ARCHI_SOC_EVENT_I2S0_TX 21
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#define ARCHI_SOC_EVENT_CPI0_RX 24
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#define ARCHI_SOC_EVENT_FILTER0_RX 28
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#define ARCHI_SOC_EVENT_FILTER0_TX 29
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#define ARCHI_SOC_EVENT_CLUSTER_ON_OFF 31
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#define ARCHI_SOC_EVENT_MSP 37
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#define ARCHI_SOC_EVENT_ICU_MODE_CHANGED 37
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#define ARCHI_SOC_EVENT_ICU_OK 37
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#define ARCHI_SOC_EVENT_ICU_DELAYED 37
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#define ARCHI_SOC_EVENT_CLUSTER_CG_OK 35
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#define ARCHI_SOC_EVENT_PICL_OK 36
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#define ARCHI_SOC_EVENT_SCU_OK 37
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#define ARCHI_SOC_EVENT_PMU_FIRST_EVENT ARCHI_SOC_EVENT_CLUSTER_ON_OFF
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#define ARCHI_SOC_EVENT_PMU_NB_EVENTS 7
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#define ARCHI_SOC_EVENT_GPIO 42
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#define ARCHI_SOC_EVENT_NB_I2S_CHANNELS 4
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#define ARCHI_SOC_EVENT_NB_UDMA_CHANNELS 19
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#define ARCHI_SOC_EVENT_SW_EVENT0 48
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#define ARCHI_SOC_EVENT_SW_EVENT1 49
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#define ARCHI_SOC_EVENT_SW_EVENT2 50
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#define ARCHI_SOC_EVENT_SW_EVENT3 51
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#define ARCHI_SOC_EVENT_SW_EVENT4 52
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#define ARCHI_SOC_EVENT_SW_EVENT5 53
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#define ARCHI_SOC_EVENT_SW_EVENT6 54
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#define ARCHI_SOC_EVENT_SW_EVENT7 55
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#define ARCHI_SOC_EVENT_NB 8
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#define ARCHI_SOC_EVENT_REF_CLK_RISE 56
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/*
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* CLUSTER EVENTS
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*/
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#define ARCHI_CL_EVT_DMA0 8
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#define ARCHI_CL_EVT_DMA1 9
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#define ARCHI_EVT_TIMER0 10
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#define ARCHI_EVT_TIMER1 11
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#define ARCHI_CL_EVT_ACC0 12
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#define ARCHI_CL_EVT_ACC1 13
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#define ARCHI_CL_EVT_ACC2 14
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#define ARCHI_CL_EVT_ACC3 15
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#define ARCHI_CL_EVT_BAR 16
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#define ARCHI_CL_EVT_MUTEX 17
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#define ARCHI_CL_EVT_DISPATCH 18
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#define ARCHI_EVT_MPU_ERROR 28
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#define ARCHI_CL_EVT_SOC_EVT 30
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#define ARCHI_EVT_SOC_FIFO 31
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/*
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* FC EVENTS
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*/
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#define ARCHI_FC_EVT_FIRST_SW 0
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#define ARCHI_FC_EVT_NB_SW 8
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#define ARCHI_FC_EVT_TIMER0_LO 10
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#define ARCHI_FC_EVT_TIMER0_HI 11
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#define ARCHI_FC_EVT_I2C_SLV_BMC 13
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#define ARCHI_FC_EVT_CLK_REF 14
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#define ARCHI_FC_EVT_GPIO 15
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#define ARCHI_FC_EVT_I2C_SLV 16
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#define ARCHI_FC_EVT_ADV_TIMER0 17
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#define ARCHI_FC_EVT_ADV_TIMER1 18
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#define ARCHI_FC_EVT_ADV_TIMER2 19
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#define ARCHI_FC_EVT_ADV_TIMER3 20
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#define ARCHI_FC_EVT_CLUSTER_NOT_BUSY 21
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#define ARCHI_FC_EVT_CLUSTER_POK 22
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#define ARCHI_FC_EVT_CLUSTER_CG_OK 23
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#define ARCHI_FC_EVT_PICL_OK 24
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#define ARCHI_FC_EVT_SCU_OK 25
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#define ARCHI_FC_EVT_SOC_EVT 26
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#define ARCHI_FC_EVT_QUEUE_ERROR 29
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#endif
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