mirror of
https://github.com/saymrwulf/pulp-runtime.git
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91 lines
No EOL
3 KiB
C
91 lines
No EOL
3 KiB
C
/*
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* Copyright (C) 2018 ETH Zurich and University of Bologna
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __ARCHI_PULP_DEFS_H__
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#define __ARCHI_PULP_DEFS_H__
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#define CHIP_MIA 0
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#define CHIP_HONEY 1
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#define CHIP_FULMINE 2
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#define CHIP_PULP4 3
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#define CHIP_PULPEVO 4
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#define CHIP_PULP4Z 5
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#define CHIP_PULP3 6
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#define CHIP_BIGPULP 7
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#define CHIP_BIGPULP_Z_7020 8
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#define CHIP_BIGPULP_Z_7045 9
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#define CHIP_BIGPULP_Z_7045_O 19
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#define CHIP_BIGPULP_Z_7045_RISCV 20
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#define CHIP_GAP 10
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#define CHIP_GAP8 10
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#define CHIP_VIVOSOC2 11
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#define CHIP_FULMINE8 12
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#define CHIP_EXACONV 13
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#define CHIP_WOLFE 14
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#define CHIP_NEURAGHE 15
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#define CHIP_PATRONUS 16
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#define CHIP_VIVOSOC3 17
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#define CHIP_VIVOSOC2_1 18
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#define CHIP_PULPINO 21
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#define CHIP_QUENTIN 22
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#define CHIP_KERBIN 23
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#define CHIP_OPRECOMPKW 24
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#define CHIP_LUPO 25
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#define CHIP_DEVCHIP 26
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#define CHIP_PULPISSIMO 27
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#define CHIP_BIGPULP_ZUX 28
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#define CHIP_PULP 29
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#define CHIP_MULTINO 30
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#define CHIP_VEGA 31
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#define CHIP_HERO_Z_7045 32
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#define CHIP_OPRECOMPKW_SA 33
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#define CHIP_OPRECOMPKW_SFLOAT 34
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#define CHIP_OPRECOMPKW_SFLOAT_SA 35
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#define CHIP_ARNOLD 36
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#define CHIP_BIGPULP_STANDALONE 37
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#define CHIP_GAP_REV1 38
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#define CHIP_USOC_V1 39
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#define CHIP_BIGPULP_JUNO 40
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#define CHIP_BIGPULP_ZU9EG 41
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#define CHIP_PULPISSIMO_V1 42
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#define CHIP_VIVOSOC3_5 43
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#define CHIP_PULP_V1 44
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#define CHIP_VIVOSOC3_1 45
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#define CHIP_GAP8_REVC 46
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#define CHIP_GAP9 47
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#define CHIP_VIVOSOC4 48
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#define CHIP_WOLFE_16 49
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#define CHIP_MARSELLUS 50
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#define CORE_OR1K_V1 0
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#define CORE_OR1K_V2 1
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#define CORE_OR1K_V3 2
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#define CORE_OR1K_V4 3
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#define CORE_OR1K_V5 4
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#define CORE_RISCV_V1 100
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#define CORE_RISCV_V2 101
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#define CORE_RISCV_V3 102
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#define CORE_RISCV_V4 103
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#define ARCHI_PLATFORM_OTHER 0
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#define ARCHI_PLATFORM_FPGA 1
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#define ARCHI_PLATFORM_RTL 2
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#define ARCHI_PLATFORM_GVSOC 3
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#define ARCHI_PLATFORM_BOARD 4
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#endif |