Corrado Bonfanti 18ab940220 Add AVS BUS support and basic test ... * Add configuration register to set AVS mode * Add connections to the SPI controller and txrx interface * Set idle level of sdio[0] signal of SPI master to '1', according to the AVS protocol * Add SPI slave device capability to trigger an event for requesting a read from master by driving low the MISO (SDATA for AVS) when AVS mode is set. This happens during tx/rx idle phases * Add basic Write commit/Read test with pulp-runtime. AVS slave is simulated in tb_avs.sv and tb_avs_fpga.sv.		2022-02-10 20:03:42 +01:00
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udma_spim_v3.h	Add AVS BUS support and basic test	2022-02-10 20:03:42 +01:00