mirror of
https://github.com/saymrwulf/pulp-runtime.git
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176 lines
5 KiB
C
176 lines
5 KiB
C
/*
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* Copyright (C) 2018 ETH Zurich and University of Bologna
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __ARCHI_UDMA_UDMA_V3_H__
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#define __ARCHI_UDMA_UDMA_V3_H__
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/*
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* Global register map
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*/
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// The UDMA register map is made of several channels, each channel area size is defined just below
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// Periph area size in log2
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#define UDMA_PERIPH_AREA_SIZE_LOG2 7
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// Periph area size
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#define UDMA_PERIPH_AREA_SIZE (1<<UDMA_PERIPH_AREA_SIZE_LOG2)
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// Channel area size in log2
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#define UDMA_CHANNEL_SIZE_LOG2 4
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// Channel area size
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#define UDMA_CHANNEL_SIZE (1<<UDMA_CHANNEL_SIZE_LOG2)
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#define UDMA_FIRST_CHANNEL_OFFSET 0x80
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// Each channel area is itself made of 3 areas
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// The offsets are given relative to the offset of the channel
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// Offset for RX part
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#define UDMA_CHANNEL_RX_OFFSET 0x00
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// Offset for TX part
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#define UDMA_CHANNEL_TX_OFFSET 0x10
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// Offset for peripheral specific part
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#define UDMA_CHANNEL_CUSTOM_OFFSET 0x20
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// For each channel, the RX and TX part have the following registers
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// The offsets are given relative to the offset of the RX or TX part
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// Start address register
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#define UDMA_CHANNEL_SADDR_OFFSET 0x0
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// Size register
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#define UDMA_CHANNEL_SIZE_OFFSET 0x4
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// Configuration register
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#define UDMA_CHANNEL_CFG_OFFSET 0x8
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// Int configuration register
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#define UDMA_CHANNEL_INTCFG_OFFSET 0xC
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// The UDMA also has a global configuration are defined here
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// Configuration area offset
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#define UDMA_CONF_OFFSET 0x0
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// Configuration area size
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#define UDMA_CONF_SIZE 0x040
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// This area contains the following registers
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// Clock-gating control register
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#define UDMA_CONF_CG_OFFSET 0x00
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// Input event control register
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#define UDMA_CONF_EVTIN_OFFSET 0x04
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/*
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* Register bitfields
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*/
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// The configuration register of the RX and TX parts for each channel can be accessed using the following bits
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#define UDMA_CHANNEL_CFG_SHADOW_BIT (5)
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#define UDMA_CHANNEL_CFG_CLEAR_BIT (5)
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#define UDMA_CHANNEL_CFG_EN_BIT (4)
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#define UDMA_CHANNEL_CFG_SIZE_BIT (1)
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#define UDMA_CHANNEL_CFG_CONT_BIT (0)
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#define UDMA_CHANNEL_CFG_SHADOW (1<<UDMA_CHANNEL_CFG_SHADOW_BIT) // Indicates if a shadow transfer is there
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#define UDMA_CHANNEL_CFG_CLEAR (1<<UDMA_CHANNEL_CFG_CLEAR_BIT) // Stop and clear all pending transfers
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#define UDMA_CHANNEL_CFG_EN (1<<UDMA_CHANNEL_CFG_EN_BIT) // Start a transfer
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#define UDMA_CHANNEL_CFG_SIZE_8 (0<<UDMA_CHANNEL_CFG_SIZE_BIT) // Configure for 8-bits transfer
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#define UDMA_CHANNEL_CFG_SIZE_16 (1<<UDMA_CHANNEL_CFG_SIZE_BIT) // Configure for 16-bits transfer
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#define UDMA_CHANNEL_CFG_SIZE_32 (2<<UDMA_CHANNEL_CFG_SIZE_BIT) // Configure for 32-bits transfer
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#define UDMA_CHANNEL_CFG_CONT (1<<UDMA_CHANNEL_CFG_CONT_BIT) // Configure for continuous mode
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/*
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* Macros
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*/
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// Returns the configuration of an input event. Several values can be ORed together to form the full configuration
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#define UDMA_CONF_EVTIN_EVT(udmaId,globalId) ((globalId)<<(udmaId*8))
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// Return the offset of a peripheral from its identifier
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#define UDMA_PERIPH_OFFSET(id) (((id)<<UDMA_PERIPH_AREA_SIZE_LOG2)+UDMA_FIRST_CHANNEL_OFFSET)
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// Returns the identifier of a peripheral from its offset
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#define UDMA_PERIPH_GET(offset) ((offset)>>UDMA_PERIPH_AREA_SIZE_LOG2)
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// Return the offset of a channel from its identifier
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#define UDMA_CHANNEL_OFFSET(id) ((id)<<UDMA_CHANNEL_SIZE_LOG2)
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// Returns the identifier of a channel from its offset
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#define UDMA_CHANNEL_GET(offset) ((offset)>>UDMA_CHANNEL_SIZE_LOG2)
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// Return the id of a channel from the peripheral id
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#define UDMA_CHANNEL_ID(id) ((id)*2)
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// Return the number of events per peripheral
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#define UDMA_NB_PERIPH_EVENTS_LOG2 2
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#define UDMA_NB_PERIPH_EVENTS (1<<UDMA_NB_PERIPH_EVENTS_LOG2)
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// Return the periph id from the channel
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#define UDMA_PERIPH_ID(id) ((id)/2)
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// Return the event id of a channel from the peripheral id
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#define UDMA_EVENT_ID(id) ((id)*UDMA_NB_PERIPH_EVENTS)
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#define ARCHI_SOC_EVENT_UDMA_RX(periph) ((periph)*2)
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#define ARCHI_SOC_EVENT_UDMA_TX(periph) ((periph)*2 + 1)
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// Define UMDA peripheral common register base address map
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#ifdef ARCHI_UDMA_HAS_SPIM
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#define ARCHI_UDMA_SPIM_RX_OFFSET 0x00
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#define ARCHI_UDMA_SPIM_TX_OFFSET 0x10
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#define ARCHI_UDMA_SPIM_CMD_OFFSET 0x20
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#define ARCHI_UDMA_SPIM_RX_EVT 0
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#define ARCHI_UDMA_SPIM_TX_EVT 1
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#define ARCHI_UDMA_SPIM_CMD_EVT 2
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#define ARCHI_UDMA_SPIM_EOT_EVT 3
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#endif
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#endif
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