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https://github.com/saymrwulf/pulp-runtime.git
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74 lines
3.5 KiB
C
74 lines
3.5 KiB
C
/*
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* Copyright (C) 2018 ETH Zurich and University of Bologna
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _ARCHI_RISCV_PCER_V1_H
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#define _ARCHI_RISCV_PCER_V1_H
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/*
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* Bit definitions for Performance counters mode registers
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*
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*/
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#define CSR_PCER_CYCLES 0 /* Count the number of cycles the core was running */
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#define CSR_PCER_INSTR 1 /* Count the number of instructions executed */
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#define CSR_PCER_LD_STALL 2 /* Number of load use hazards */
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#define CSR_PCER_JMP_STALL 3 /* Number of jump register hazards */
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#define CSR_PCER_IMISS 4 /* Cycles waiting for instruction fetches. i.e. the number of instructions wasted due to non-ideal caches */
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#define CSR_PCER_LD 5 /* Number of memory loads executed. Misaligned accesses are counted twice */
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#define CSR_PCER_ST 6 /* Number of memory stores executed. Misaligned accesses are counted twice */
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#define CSR_PCER_JUMP 7 /* Number of jump instructions seen, i.e. j, jr, jal, jalr */
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#define CSR_PCER_BRANCH 8 /* Number of branch instructions seen, i.e. bf, bnf */
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#define CSR_PCER_TAKEN_BRANCH 9 /* Number of taken branch instructions seen, i.e. bf, bnf */
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#define CSR_PCER_RVC 10 /* Number of compressed instructions */
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#define CSR_PCER_ELW 11 /* Cycles wasted due to ELW instruction */
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#define CSR_PCER_LD_EXT 12 /* Number of memory loads to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */
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#define CSR_PCER_ST_EXT 13 /* Number of memory stores to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */
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#define CSR_PCER_LD_EXT_CYC 14 /* Cycles used for memory loads to EXT. Every non-TCDM access is considered external */
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#define CSR_PCER_ST_EXT_CYC 15 /* Cycles used for memory stores to EXT. Every non-TCDM access is considered external */
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#define CSR_PCER_TCDM_CONT 16 /* Cycles wasted due to TCDM/log-interconnect contention */
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#define CSR_PCER_NB_EVENTS 17
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#define CSR_PCER_NB_INTERNAL_EVENTS 12
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#define CSR_NB_PCCR 31
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// Gives from the event ID, the HW mask that can be stored (with an OR with other events mask) to the PCER
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#define CSR_PCER_EVENT_MASK(eventId) (1<<(eventId))
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#define CSR_PCER_ALL_EVENTS_MASK 0xffffffff
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#define CSR_PCMR_ACTIVE 0x1 /* Activate counting */
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#define CSR_PCMR_SATURATE 0x2 /* Activate saturation */
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#define CSR_PCER_NAME(id) \
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( id == 0 ? "Cycles" : \
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id == 1 ? "Instructions" : \
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id == 2 ? "LD_Stall" : \
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id == 3 ? "Jmp_Stall" : \
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id == 4 ? "IMISS" : \
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id == 5 ? "LD" : \
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id == 6 ? "ST" : \
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id == 7 ? "JUMP" : \
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id == 8 ? "BRANCH" : \
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id == 9 ? "TAKEN_BRANCH" : \
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id == 10 ? "RVC" : \
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id == 11 ? "ELW" : \
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id == 12 ? "LD_EXT" : \
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id == 13 ? "ST_EXT" : \
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id == 14 ? "LD_EXT_CYC" : \
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id == 15 ? "ST_EXT_CYC" : \
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id == 16 ? "TCDM_CONT" : \
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"NA")
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#endif
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