/* * Copyright (C) 2018 ETH Zurich and University of Bologna * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __ARCHI_PULP_DEFS_H__ #define __ARCHI_PULP_DEFS_H__ #define CHIP_MIA 0 #define CHIP_HONEY 1 #define CHIP_FULMINE 2 #define CHIP_PULP4 3 #define CHIP_PULPEVO 4 #define CHIP_PULP4Z 5 #define CHIP_PULP3 6 #define CHIP_BIGPULP 7 #define CHIP_BIGPULP_Z_7020 8 #define CHIP_BIGPULP_Z_7045 9 #define CHIP_BIGPULP_Z_7045_O 19 #define CHIP_BIGPULP_Z_7045_RISCV 20 #define CHIP_GAP 10 #define CHIP_GAP8 10 #define CHIP_VIVOSOC2 11 #define CHIP_FULMINE8 12 #define CHIP_EXACONV 13 #define CHIP_WOLFE 14 #define CHIP_NEURAGHE 15 #define CHIP_PATRONUS 16 #define CHIP_VIVOSOC3 17 #define CHIP_VIVOSOC2_1 18 #define CHIP_PULPINO 21 #define CHIP_QUENTIN 22 #define CHIP_KERBIN 23 #define CHIP_OPRECOMPKW 24 #define CHIP_LUPO 25 #define CHIP_DEVCHIP 26 #define CHIP_PULPISSIMO 27 #define CHIP_BIGPULP_ZUX 28 #define CHIP_PULP 29 #define CHIP_MULTINO 30 #define CHIP_VEGA 31 #define CHIP_HERO_Z_7045 32 #define CHIP_OPRECOMPKW_SA 33 #define CHIP_OPRECOMPKW_SFLOAT 34 #define CHIP_OPRECOMPKW_SFLOAT_SA 35 #define CHIP_ARNOLD 36 #define CHIP_BIGPULP_STANDALONE 37 #define CHIP_GAP_REV1 38 #define CHIP_USOC_V1 39 #define CHIP_BIGPULP_JUNO 40 #define CHIP_BIGPULP_ZU9EG 41 #define CHIP_PULPISSIMO_V1 42 #define CHIP_VIVOSOC3_5 43 #define CHIP_PULP_V1 44 #define CHIP_VIVOSOC3_1 45 #define CHIP_GAP8_REVC 46 #define CHIP_GAP9 47 #define CHIP_VIVOSOC4 48 #define CHIP_WOLFE_16 49 #define CHIP_MARSELLUS 50 #define CORE_OR1K_V1 0 #define CORE_OR1K_V2 1 #define CORE_OR1K_V3 2 #define CORE_OR1K_V4 3 #define CORE_OR1K_V5 4 #define CORE_RISCV_V1 100 #define CORE_RISCV_V2 101 #define CORE_RISCV_V3 102 #define CORE_RISCV_V4 103 #define ARCHI_PLATFORM_OTHER 0 #define ARCHI_PLATFORM_FPGA 1 #define ARCHI_PLATFORM_RTL 2 #define ARCHI_PLATFORM_GVSOC 3 #define ARCHI_PLATFORM_BOARD 4 #endif