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https://github.com/saymrwulf/pulp-runtime.git
synced 2026-05-26 22:35:49 +00:00
Add performance section code
This commit is contained in:
Michael Rogenmoser
parent
5e8e693242
commit
f754455e34
5 changed files with 121 additions and 5 deletions
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@ -88,6 +88,7 @@ extern "C" {
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#define HMR_REGISTERS_TMR_CONFIG_RELOAD_SETBACK_BIT 2
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#define HMR_REGISTERS_TMR_CONFIG_RAPID_RECOVERY_BIT 3
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#define HMR_REGISTERS_TMR_CONFIG_FORCE_RESYNCH_BIT 4
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#define HMR_REGISTERS_TMR_CONFIG_SYNCH_REQ_BIT 5
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#ifdef __cplusplus
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} // extern "C"
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@ -143,6 +144,7 @@ extern "C" {
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#define HMR_DMR_REGS_DMR_CONFIG_REG_OFFSET 0x4
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#define HMR_DMR_REGS_DMR_CONFIG_RAPID_RECOVERY_BIT 0
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#define HMR_DMR_REGS_DMR_CONFIG_FORCE_RECOVERY_BIT 1
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#define HMR_DMR_REGS_DMR_CONFIG_SETBACK_BIT 1
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// Address for the last checkpoint.
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#define HMR_DMR_REGS_CHECKPOINT_ADDR_REG_OFFSET 0x8
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@ -175,6 +177,7 @@ extern "C" {
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#define HMR_TMR_REGS_TMR_CONFIG_RELOAD_SETBACK_BIT 2
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#define HMR_TMR_REGS_TMR_CONFIG_RAPID_RECOVERY_BIT 3
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#define HMR_TMR_REGS_TMR_CONFIG_FORCE_RESYNCH_BIT 4
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#define HMR_TMR_REGS_TMR_CONFIG_SYNCH_REQ_BIT 5
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#ifdef __cplusplus
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} // extern "C"
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@ -26,6 +26,7 @@
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#define CSR_PCMR_ACTIVE 0x1
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#define SR_MTVEC 0x305
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#define CSR_MIE 0x304
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@ -153,24 +153,30 @@ static inline void hmr_disable_tmr(unsigned int cid, unsigned int tmr_id) {
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pulp_write32(ARCHI_HMR_GLOBAL_ADDR(cid) + HMR_TMR_OFFSET + HMR_TMR_INCREMENT*tmr_id + HMR_TMR_REGS_TMR_ENABLE_REG_OFFSET, 0);
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}
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static inline void hmr_set_tmr_config(unsigned int cid, unsigned int tmr_id, bool delay_resynch, bool setback, bool reload_setback, bool rapid_recovery) {
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static inline void hmr_set_tmr_config(unsigned int cid, unsigned int tmr_id, bool delay_resynch, bool setback, bool reload_setback, bool rapid_recovery, bool synch_req) {
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pulp_write32(ARCHI_HMR_GLOBAL_ADDR(0) + HMR_TMR_OFFSET + HMR_TMR_INCREMENT*tmr_id + HMR_TMR_REGS_TMR_CONFIG_REG_OFFSET,
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(delay_resynch ? 1<<HMR_TMR_REGS_TMR_CONFIG_DELAY_RESYNCH_BIT : 0) |
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(setback ? 1<<HMR_TMR_REGS_TMR_CONFIG_SETBACK_BIT : 0) |
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(reload_setback ? 1<<HMR_TMR_REGS_TMR_CONFIG_RELOAD_SETBACK_BIT : 0) |
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(rapid_recovery ? 1<<HMR_TMR_REGS_TMR_CONFIG_RAPID_RECOVERY_BIT : 0));
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(rapid_recovery ? 1<<HMR_TMR_REGS_TMR_CONFIG_RAPID_RECOVERY_BIT : 0) |
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(synch_req ? 1<<HMR_TMR_REGS_TMR_CONFIG_SYNCH_REQ_BIT : 0));
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}
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static inline unsigned int hmr_get_tmr_config(unsigned int cid, unsigned int tmr_id) {
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return pulp_read32(ARCHI_HMR_GLOBAL_ADDR(0) + HMR_TMR_OFFSET + HMR_TMR_INCREMENT*tmr_id + HMR_TMR_REGS_TMR_CONFIG_REG_OFFSET);
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}
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static inline void hmr_set_tmr_config_all(unsigned int cid, bool delay_resynch, bool setback, bool reload_setback, bool rapid_recovery) {
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static inline void hmr_set_tmr_config_bare(unsigned int cid, unsigned int tmr_id, unsigned int config) {
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pulp_write32(ARCHI_HMR_GLOBAL_ADDR(0) + HMR_TMR_OFFSET + HMR_TMR_INCREMENT*tmr_id + HMR_TMR_REGS_TMR_CONFIG_REG_OFFSET, config);
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}
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static inline void hmr_set_tmr_config_all(unsigned int cid, bool delay_resynch, bool setback, bool reload_setback, bool rapid_recovery, bool synch_req) {
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pulp_write32(ARCHI_HMR_GLOBAL_ADDR(0) + HMR_TOP_OFFSET + HMR_REGISTERS_TMR_CONFIG_REG_OFFSET,
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(delay_resynch ? 1<<HMR_REGISTERS_TMR_CONFIG_DELAY_RESYNCH_BIT : 0) |
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(setback ? 1<<HMR_REGISTERS_TMR_CONFIG_SETBACK_BIT : 0) |
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(reload_setback ? 1<<HMR_REGISTERS_TMR_CONFIG_RELOAD_SETBACK_BIT : 0) |
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(rapid_recovery ? 1<<HMR_REGISTERS_TMR_CONFIG_RAPID_RECOVERY_BIT : 0));
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(rapid_recovery ? 1<<HMR_REGISTERS_TMR_CONFIG_RAPID_RECOVERY_BIT : 0) |
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(synch_req ? 1<<HMR_REGISTERS_TMR_CONFIG_SYNCH_REQ_BIT : 0));
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}
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static inline void hmr_force_tmr_resynch(unsigned int cid, unsigned int tmr_id) {
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@ -35,8 +35,31 @@ typedef enum {
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PI_FREQ_NB_DOMAINS = 3
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} pi_freq_domain_e;
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#ifdef ARCHI_HMR
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void __attribute__((naked)) pos_hmr_store_part_to_stack();
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void __attribute((naked)) pos_hmr_store_rest_to_stack();
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void __attribute((interrupt)) pos_hmr_load_part_from_stack();
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void __attribute__((naked)) pos_hmr_store_state_to_stack();
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void __attribute__((naked)) pos_hmr_load_state_from_stack();
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void __attribute__((interrupt)) pos_hmr_sw_reload();
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void __attribute__((naked)) pos_hmr_tmr_irq();
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void __attribute__((naked)) pos_hmr_synch();
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void __attribute__((naked)) pos_hmr_tmr_synch_entry();
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void __attribute__((naked)) pos_hmr_tmr_synch_exit();
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void __attribute__((naked)) pos_hmr_tmr_synch();
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void __attribute__((naked)) pos_hmr_dmr_synch();
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int hmr_tmr_critical_section(int (*function_handle)());
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int hmr_dmr_critical_section(int (*function_handle)());
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void hmr_tmr_performance_section(void (*function_handle)());
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void hmr_tmr_perf_setup_sp();
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#endif
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#ifdef ARCHI_HAS_CLUSTER
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extern L1_DATA char *cluster_stacks;
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void cluster_start(int cid, int (*entry)());
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void cluster_entry_stub();
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@ -409,7 +409,7 @@ void __attribute__((naked)) pos_hmr_synch() {
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pos_hmr_sw_reload();
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}
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void __attribute__((naked)) pos_hmr_tmr_synch() {
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void __attribute__((naked)) pos_hmr_tmr_synch_entry() {
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pos_hmr_store_part_to_stack();
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pos_hmr_store_rest_to_stack();
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@ -422,7 +422,9 @@ void __attribute__((naked)) pos_hmr_tmr_synch() {
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"add t0, t0, t1 \n\t"
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"sw sp, " QU(HMR_CORE_REGS_SP_STORE_REG_OFFSET) "(t0) \n\t"
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: : : "memory");
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}
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void __attribute__((naked)) pos_hmr_tmr_synch_exit() {
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// enter barrier -> this should lock the cores together
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eu_bar_trig_wait_clr(eu_bar_addr(TMR_BARRIER_ID(TMR_GROUP_ID(core_id()))));
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@ -438,6 +440,11 @@ void __attribute__((naked)) pos_hmr_tmr_synch() {
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pos_hmr_sw_reload();
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}
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void __attribute__((naked)) pos_hmr_tmr_synch() {
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pos_hmr_tmr_synch_entry();
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pos_hmr_tmr_synch_exit();
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}
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void __attribute__((naked)) pos_hmr_dmr_synch() {
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pos_hmr_store_part_to_stack();
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@ -499,6 +506,82 @@ int hmr_dmr_critical_section(int (*function_handle)()) {
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}
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}
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void hmr_tmr_performance_section(void (*function_handle)()) {
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__asm__ __volatile__(
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"la ra, pos_hmr_perf_help\n\t"
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"csrw 0x341, ra\n\t"
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);
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volatile unsigned int tmr_group_id = TMR_GROUP_ID(core_id());
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unsigned int tmr_config = hmr_get_tmr_config(0, tmr_group_id);
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hmr_set_tmr_config_bare(0, tmr_group_id, tmr_config & ~(1<<HMR_REGISTERS_TMR_CONFIG_SETBACK_BIT));
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register unsigned int my_core_id;
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hmr_disable_tmr(0, tmr_group_id);
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__asm__ __volatile__(
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"csrr %[core_id], 0xf14 \n\t" // Read core id
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: [core_id] "=r" (my_core_id) : : "memory");
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// volatile unsigned int my_core_id = core_id();
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if (TMR_IS_MAIN_CORE(my_core_id)) {
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hmr_set_tmr_config_bare(0, TMR_GROUP_ID(my_core_id), tmr_config);
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} else {
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// get sp from tmr reg, assumes a5 is empty
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__asm__ __volatile__(
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// "csrr a5, 0xf14 \n\t" // Read core id
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"li sp, " QU(ARCHI_HMR_ADDR + HMR_CORE_OFFSET) " \n\t"
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"andi %[core_id], %[core_id], 0x01f \n\t"
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"sll %[core_id], %[core_id], " QU(HMR_CORE_SLL) " \n\t"
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"add %[core_id], %[core_id], sp \n\t"
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"lw sp, " QU(HMR_CORE_REGS_SP_STORE_REG_OFFSET) "(%[core_id]) \n\t"
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: : [core_id] "r" (my_core_id) : "memory");
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eu_evt_maskSet((1<<PULP_DISPATCH_EVENT) | (1<<PULP_MUTEX_EVENT) | (1<<PULP_HW_BAR_EVENT));
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}
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function_handle();
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if (TMR_IS_MAIN_CORE(core_id())) {
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pulp_write32(ARCHI_HMR_ADDR + HMR_TMR_OFFSET + HMR_TMR_INCREMENT*core_id() + HMR_TMR_REGS_TMR_ENABLE_REG_OFFSET, 1<<HMR_TMR_REGS_TMR_ENABLE_TMR_ENABLE_BIT);
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#if !defined(ARCHI_HMR_FORCE_RAPID) || !defined(ARCHI_HMR_NO_RAPID_RECOVERY)
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// TODO check Rapid
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#elif defined(ARCHI_HMR_FORCE_RAPID)
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#else
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#endif
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pos_hmr_tmr_synch_entry();
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// Ugly hack allows for proper cleanup of stack by function
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__asm__ __volatile__(
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"auipc t1, 0\n\t"
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"addi t1, t1, 12\n\t" // Add instruction increment to after pos_hmr_tmr_synch_exit call
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"sw t1, 0x78(sp) \n\t" // Update mepc on stack for return later
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"j pos_hmr_tmr_synch_exit\n\t"
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);
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} else {
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__asm__ __volatile__ (
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"j pos_hmr_tmr_synch_exit\n\t");
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}
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}
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void __attribute__((naked)) pos_hmr_perf_help() {}
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void hmr_tmr_perf_setup_sp() {
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unsigned int core_id_1 = TMR_CORE_ID(TMR_GROUP_ID(core_id()), 1);
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unsigned int core_id_2 = TMR_CORE_ID(TMR_GROUP_ID(core_id()), 2);
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unsigned int *extra_sp_1 = (unsigned int *)(ARCHI_HMR_ADDR + HMR_CORE_OFFSET + (core_id_1 << HMR_CORE_SLL) + HMR_CORE_REGS_SP_STORE_REG_OFFSET);
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unsigned int *extra_sp_2 = (unsigned int *)(ARCHI_HMR_ADDR + HMR_CORE_OFFSET + (core_id_2 << HMR_CORE_SLL) + HMR_CORE_REGS_SP_STORE_REG_OFFSET);
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eu_bar_setup(eu_bar_addr(TMR_BARRIER_ID(TMR_GROUP_ID(core_id()))), TMR_BARRIER_SETUP(TMR_GROUP_ID(core_id())));
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pulp_write32(extra_sp_1, (unsigned int)((core_id_1+1)*CLUSTER_STACK_SIZE + cluster_stacks));
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pulp_write32(extra_sp_2, (unsigned int)((core_id_2+1)*CLUSTER_STACK_SIZE + cluster_stacks));
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}
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// void pos_hmr_tmr_unsync() {
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// // Update event unit mask
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