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https://github.com/saymrwulf/pulp-runtime.git
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add udma_sdio header file
This commit is contained in:
Mattia Sinigaglia
parent
c361662ed5
commit
eb664a6dd6
2 changed files with 226 additions and 0 deletions
112
include/archi/udma/sdio/udma_sdio.h
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112
include/archi/udma/sdio/udma_sdio.h
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/*
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* Copyright (C) 2018 ETH Zurich and University of Bologna
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __ARCHI_UDMA_UDMA_SDIO_H__
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#define __ARCHI_UDMA_UDMA_SDIO_H__
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/* -------------------------------------------------------------------------
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-- SDIO CMDs
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-------------------------------------------------------------------------
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See page 49 (60 pdf numbering) of Physical Layer Simplified Spec Ver2.00
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*/
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#define CMD0 0x000 // GO_IDLE_STATE
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#define CMD2 0x200 // ALL_SEND_CID
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#define CMD3 0x300 // SEND_RELATIVE_ADDR
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#define ACMD6 0x600
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#define CMD7 0x700
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#define CMD8 0x800
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#define CMD55 0x3700
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#define ACMD41 0x2900 // ACMD, need to be used after APP_SPEC_CMD
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#define CMD8 0x800
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#define CMD9 0x900
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#define CMD10 0x0A00
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#define CMD11 0x0B00
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#define CMD12 0x0C00
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#define CMD13 0x0D00
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#define CMD16 0x1000
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#define CMD17 0x1100 // READ_SINGLE_BLOCK
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#define CMD18 0x1200
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#define CMD24 0x1800 // WRITE_SINGLE_BLOCK
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#define CMD25 0x1900 // WRITE_MULTIPLE_BLOCK
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//UDMA_SDIO_CMD_RESP_TYPE
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#define RSP_48_CRC 0x1
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#define RSP_48_NO_CRC 0x2
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#define RSP_136 0x3
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#define RSP_48_BUSY 0x4
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//SDIO_CMD_ERR_STATUS TYPES
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#define UDMA_SDIO_NO_ERR_CMD 0
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#define UDMA_SDIO_RESP_TIME_OUT_CMD 1
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#define UDMA_SDIO_RESP_WRONG_DIR_CMD 2
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#define UDMA_SDIO_RESP_BUSY_TOUT_CMD 3
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//SDIO_DATA_ERR_STATUS TYPES
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#define UDMA_SDIO_NO_ERR_DATA 0
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#define UDMA_SDIO_RESP_TIME_OUT_DATA 1
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//UDMA_SDIO_CMD_OP field
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#define UDMA_SDIO_CMD_RESP_TYPE_OFFSET 0
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#define UDMA_SDIO_CMD_OP_OFFSET 8
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//UDMA_SDIO_CMD_ARG field
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#define UDMA_SDIO_CMD_ARG_OFFSET 0
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//UDMA_SDIO_DATA_SETUP field
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#define UDMA_SDIO_DATA_EN_OFFSET 0
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#define UDMA_SDIO_DATA_RWN_OFFSET 1
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#define UDMA_SDIO_DATA_QUAD_OFFSET 2
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#define UDMA_SDIO_BLOCK_NUM_OFFSET 8
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#define UDMA_SDIO_BLOCK_SIZE_OFFSET 16
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//UDMA_SDIO_STATUS field
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#define UDMA_SDIO_EOT_OFFSET 0
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#define UDMA_SDIO_ERROR_OFFSET 1
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#define UDMA_SDIO_CMD_ERR_STATUS_OFFSET 16
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#define UDMA_SDIO_DATA_ERR_STATUS_OFFSET 24
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//UDMA_SDIO_STOPCMD_OP field
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#define UDMA_SDIO_STOPCMD_RSP_TYPE_OFFSET 0
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#define UDMA_SDIO_STOPCMD_OPTYPE_OFFSET 8
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//SDIO registers
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#define UDMA_SDIO_OFFSET(id) UDMA_PERIPH_OFFSET(ARCHI_UDMA_SDIO_ID(id))
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#define UDMA_SDIO_RX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + UDMA_CHANNEL_RX_OFFSET)
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#define UDMA_SDIO_RX_SIZE(id) (UDMA_SDIO_RX_ADDR(id) + UDMA_CHANNEL_SIZE_OFFSET)
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#define UDMA_SDIO_RX_CFG(id) (UDMA_SDIO_RX_ADDR(id) + UDMA_CHANNEL_CFG_OFFSET)
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#define UDMA_SDIO_TX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + UDMA_CHANNEL_TX_OFFSET)
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#define UDMA_SDIO_TX_SIZE(id) (UDMA_SDIO_TX_ADDR(id) + UDMA_CHANNEL_SIZE_OFFSET)
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#define UDMA_SDIO_TX_CFG(id) (UDMA_SDIO_TX_ADDR(id) + UDMA_CHANNEL_CFG_OFFSET)
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#define UDMA_SDIO_CMD_OP(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x20) // R/W
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#define UDMA_SDIO_CMD_ARG(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x24) // R/W
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#define UDMA_SDIO_DATA_SETUP(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x28) // W
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#define UDMA_SDIO_START(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x2C) // W
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#define UDMA_SDIO_RSP0(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x30) // R
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#define UDMA_SDIO_RSP1(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x34) // R
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#define UDMA_SDIO_RSP2(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x38) // R
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#define UDMA_SDIO_RSP3(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x3C) // R
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#define UDMA_SDIO_CLK_DIV(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x40) // R/W
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#define UDMA_SDIO_STATUS(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x44) // R/W
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#define UDMA_SDIO_STOPCMD_OP(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x48) // R/W
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#define UDMA_SDIO_STOPCMD_ARG(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x52) // R/W
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#endif
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114
include/hal/udma/sdio/udma_sdio.h
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114
include/hal/udma/sdio/udma_sdio.h
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@ -0,0 +1,114 @@
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/*
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* Copyright (C) 2018 ETH Zurich and University of Bologna
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __HAL_UDMA_UDMA_SDIO_H__
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#define __HAL_UDMA_UDMA_SDIO_H__
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#include "archi/udma/sdio/udma_sdio.h"
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/* -------------------------------------------------------------------------
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-- SDIO CMDs
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-------------------------------------------------------------------------
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See page 49 (60 pdf numbering) of Physical Layer Simplified Spec Ver2.00
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*/
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#define CMD0 0x000 // GO_IDLE_STATE
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#define CMD2 0x200 // ALL_SEND_CID
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#define CMD3 0x300 // SEND_RELATIVE_ADDR
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#define ACMD6 0x600
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#define CMD7 0x700
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#define CMD8 0x800
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#define CMD55 0x3700
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#define ACMD41 0x2900 // ACMD, need to be used after APP_SPEC_CMD
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#define CMD8 0x800
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#define CMD9 0x900
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#define CMD10 0x0A00
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#define CMD11 0x0B00
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#define CMD12 0x0C00
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#define CMD13 0x0D00
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#define CMD16 0x1000
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#define CMD17 0x1100 // READ_SINGLE_BLOCK
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#define CMD18 0x1200
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#define CMD24 0x1800 // WRITE_SINGLE_BLOCK
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#define CMD25 0x1900 // WRITE_MULTIPLE_BLOCK
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//UDMA_SDIO_CMD_RESP_TYPE
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#define RSP_48_CRC 0x1
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#define RSP_48_NO_CRC 0x2
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#define RSP_136 0x3
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#define RSP_48_BUSY 0x4
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//SDIO_CMD_ERR_STATUS TYPES
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#define UDMA_SDIO_NO_ERR_CMD 0
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#define UDMA_SDIO_RESP_TIME_OUT_CMD 1
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#define UDMA_SDIO_RESP_WRONG_DIR_CMD 2
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#define UDMA_SDIO_RESP_BUSY_TOUT_CMD 3
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//SDIO_DATA_ERR_STATUS TYPES
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#define UDMA_SDIO_NO_ERR_DATA 0
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#define UDMA_SDIO_RESP_TIME_OUT_DATA 1
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//UDMA_SDIO_CMD_OP field
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#define UDMA_SDIO_CMD_RESP_TYPE_OFFSET 0
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#define UDMA_SDIO_CMD_OP_OFFSET 8
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//UDMA_SDIO_CMD_ARG field
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#define UDMA_SDIO_CMD_ARG_OFFSET 0
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//UDMA_SDIO_DATA_SETUP field
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#define UDMA_SDIO_DATA_EN_OFFSET 0
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#define UDMA_SDIO_DATA_RWN_OFFSET 1
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#define UDMA_SDIO_DATA_QUAD_OFFSET 2
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#define UDMA_SDIO_BLOCK_NUM_OFFSET 8
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#define UDMA_SDIO_BLOCK_SIZE_OFFSET 16
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//UDMA_SDIO_STATUS field
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#define UDMA_SDIO_EOT_OFFSET 0
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#define UDMA_SDIO_ERROR_OFFSET 1
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#define UDMA_SDIO_CMD_ERR_STATUS_OFFSET 16
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#define UDMA_SDIO_DATA_ERR_STATUS_OFFSET 24
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//UDMA_SDIO_STOPCMD_OP field
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#define UDMA_SDIO_STOPCMD_RSP_TYPE_OFFSET 0
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#define UDMA_SDIO_STOPCMD_OPTYPE_OFFSET 8
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//SDIO registers
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#define UDMA_SDIO_OFFSET(id) UDMA_PERIPH_OFFSET(ARCHI_UDMA_SDIO_ID(id))
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#define UDMA_SDIO_RX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + UDMA_CHANNEL_RX_OFFSET)
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#define UDMA_SDIO_RX_SIZE(id) (UDMA_SDIO_RX_ADDR(id) + UDMA_CHANNEL_SIZE_OFFSET)
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#define UDMA_SDIO_RX_CFG(id) (UDMA_SDIO_RX_ADDR(id) + UDMA_CHANNEL_CFG_OFFSET)
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#define UDMA_SDIO_TX_ADDR(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + UDMA_CHANNEL_TX_OFFSET)
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#define UDMA_SDIO_TX_SIZE(id) (UDMA_SDIO_TX_ADDR(id) + UDMA_CHANNEL_SIZE_OFFSET)
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#define UDMA_SDIO_TX_CFG(id) (UDMA_SDIO_TX_ADDR(id) + UDMA_CHANNEL_CFG_OFFSET)
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#define UDMA_SDIO_CMD_OP(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x20) // R/W
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#define UDMA_SDIO_CMD_ARG(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x24) // R/W
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#define UDMA_SDIO_DATA_SETUP(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x28) // W
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#define UDMA_SDIO_START(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x2C) // W
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#define UDMA_SDIO_RSP0(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x30) // R
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#define UDMA_SDIO_RSP1(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x34) // R
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#define UDMA_SDIO_RSP2(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x38) // R
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#define UDMA_SDIO_RSP3(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x3C) // R
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#define UDMA_SDIO_CLK_DIV(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x40) // R/W
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#define UDMA_SDIO_STATUS(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x44) // R/W
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#define UDMA_SDIO_STOPCMD_OP(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x48) // R/W
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#define UDMA_SDIO_STOPCMD_ARG(id) (ARCHI_UDMA_ADDR + UDMA_SDIO_OFFSET(id) + 0x52) // R/W
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#endif
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