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Update sp storage register

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Michael Rogenmoser 2023-02-03 13:53:27 +01:00
parent 3a48d6e1a1
commit d7599d8b68
2 changed files with 12 additions and 9 deletions
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9
include/archi/hmr/hmr_v1.h
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@ -24,7 +24,8 @@
#define HMR_DMR_OFFSET 0x200
#define HMR_TMR_OFFSET 0x300
#define HMR_CORE_INCREMENT 0x008
#define HMR_CORE_INCREMENT 0x010
#define HMR_CORE_SLL 0x004
#define HMR_DMR_INCREMENT 0x010
#define HMR_DMR_SLL 0x004
#define HMR_TMR_INCREMENT 0x010
@ -114,6 +115,9 @@ extern "C" {
// Mismatches of the core
#define HMR_CORE_REGS_MISMATCHES_REG_OFFSET 0x4
// Stack Pointer storage register
#define HMR_CORE_REGS_SP_STORE_REG_OFFSET 0x8
#ifdef __cplusplus
} // extern "C"
#endif
@ -172,9 +176,6 @@ extern "C" {
#define HMR_TMR_REGS_TMR_CONFIG_RAPID_RECOVERY_BIT 3
#define HMR_TMR_REGS_TMR_CONFIG_FORCE_RESYNCH_BIT 4
// Stack Pointer storage register
#define HMR_TMR_REGS_SP_STORE_REG_OFFSET 0x8
#ifdef __cplusplus
} // extern "C"
#endif

12
kernel/hmr_synch.c
View file

@ -161,10 +161,11 @@ void __attribute__((interrupt)) pos_hmr_tmr_reload() {
__asm__ __volatile__(
"csrr t0, 0xf14 \n\t" // Read core id
"li t1, " QU(ARCHI_HMR_ADDR) " \n\t"
"addi t1, t1, " QU(HMR_CORE_OFFSET) " \n\t"
"andi t0, t0, 0x01f \n\t"
"sll t0, t0, " QU(HMR_TMR_SLL) " \n\t"
"sll t0, t0, " QU(HMR_CORE_SLL) " \n\t"
"add t0, t0, t1 \n\t"
"lw sp, " QU(HMR_TMR_REGS_SP_STORE_REG_OFFSET) "(t0) \n\t"
"lw sp, " QU(HMR_CORE_REGS_SP_STORE_REG_OFFSET) "(t0) \n\t"
"mv ra, t0 \n\t"
: : : "memory");
@ -172,7 +173,7 @@ void __attribute__((interrupt)) pos_hmr_tmr_reload() {
// set tmr reg to 0
__asm__ __volatile__(
"sw zero, " QU(HMR_TMR_REGS_SP_STORE_REG_OFFSET) "(ra) \n\t"
"sw zero, " QU(HMR_CORE_REGS_SP_STORE_REG_OFFSET) "(ra) \n\t"
"lw ra, -" QU(HMR_STATE_ALLOC_SIZE) "(sp) \n\t"
: : : "memory");
@ -187,10 +188,11 @@ void __attribute__((naked)) pos_hmr_tmr_irq() {
__asm__ __volatile__(
"csrr t0, 0xf14 \n\t" // Read core id
"li t1, " QU(ARCHI_HMR_ADDR) " \n\t"
"addi t1, t1, " QU(HMR_CORE_OFFSET) " \n\t"
"andi t0, t0, 0x01f \n\t"
"sll t0, t0, " QU(HMR_TMR_SLL) " \n\t"
"sll t0, t0, " QU(HMR_CORE_SLL) " \n\t"
"add t0, t0, t1 \n\t"
"sw sp, " QU(HMR_TMR_REGS_SP_STORE_REG_OFFSET) "(t0) \n\t"
"sw sp, " QU(HMR_CORE_REGS_SP_STORE_REG_OFFSET) "(t0) \n\t"
: : : "memory");
// several nops to delay and allow for core reset