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Update critical section code for functionality

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This commit is contained in:
Michael Rogenmoser 2023-02-10 11:16:38 +01:00
parent 10208561c0
commit 90a4c57a42
4 changed files with 26 additions and 9 deletions
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14
include/hal/hmr/hmr_v1.h
View file

@ -121,6 +121,16 @@ static inline void hmr_enable_tmr(unsigned int cid, unsigned int tmr_id) {
pulp_write32(ARCHI_HMR_GLOBAL_ADDR(cid) + HMR_TMR_OFFSET + HMR_TMR_INCREMENT*tmr_id + HMR_TMR_REGS_TMR_ENABLE_REG_OFFSET, 1<<HMR_TMR_REGS_TMR_ENABLE_TMR_ENABLE_BIT);
}
static inline void hmr_self_enable_tmr() {
if (TMR_IS_MAIN_CORE(core_id())) {
eu_bar_setup(eu_bar_addr(TMR_BARRIER_ID(TMR_GROUP_ID(core_id()))), TMR_BARRIER_SETUP(TMR_GROUP_ID(core_id())));
pulp_write32(ARCHI_HMR_ADDR + HMR_TMR_OFFSET + HMR_TMR_INCREMENT*core_id() + HMR_TMR_REGS_TMR_ENABLE_REG_OFFSET, 1<<HMR_TMR_REGS_TMR_ENABLE_TMR_ENABLE_BIT);
while (hmr_get_core_status(0, core_id()) != 1<<HMR_CORE_REGS_CURRENT_MODE_TRIPLE_BIT) {
asm volatile ("nop");
}
}
}
static inline void hmr_disable_all_tmr(unsigned int cid) {
hmr_set_tmr_status_all(cid, 0);
}
@ -137,6 +147,10 @@ static inline void hmr_set_tmr_config(unsigned int cid, unsigned int tmr_id, boo
(rapid_recovery ? 1<<HMR_TMR_REGS_TMR_CONFIG_RAPID_RECOVERY_BIT : 0));
}
static inline unsigned int hmr_get_tmr_config(unsigned int cid, unsigned int tmr_id) {
return pulp_read32(ARCHI_HMR_GLOBAL_ADDR(0) + HMR_TMR_OFFSET + HMR_TMR_INCREMENT*tmr_id + HMR_TMR_REGS_TMR_CONFIG_REG_OFFSET);
}
static inline void hmr_set_tmr_config_all(unsigned int cid, bool delay_resynch, bool setback, bool reload_setback, bool rapid_recovery) {
pulp_write32(ARCHI_HMR_GLOBAL_ADDR(0) + HMR_TOP_OFFSET + HMR_REGISTERS_TMR_CONFIG_REG_OFFSET,
(delay_resynch ? 1<<HMR_REGISTERS_TMR_CONFIG_DELAY_RESYNCH_BIT : 0) |

8
kernel/cluster.c
View file

@ -41,7 +41,13 @@ static void cluster_core_init()
eu_evt_maskSet((1<<PULP_DISPATCH_EVENT) | (1<<PULP_MUTEX_EVENT) | (1<<PULP_HW_BAR_EVENT));
#ifdef ARCHI_HMR
eu_irq_maskSet(1<<24 | 1<<23); // Enable resynch and synch requests
// Enable resynch and synch requests
eu_irq_maskSet(1<<24 | 1<<23);
rt_irq_set_handler(24, pos_hmr_tmr_irq);
rt_irq_set_handler(23, pos_hmr_tmr_synch);
hal_spr_write(0x304, 1<<24|1<<23);
hal_irq_enable();
eu_bar_setup(eu_bar_addr(0), hmr_get_active_cores(0));
#else
eu_bar_setup(eu_bar_addr(0), (1<<ARCHI_CLUSTER_NB_PE) - 1);

2
kernel/crt0.S
View file

@ -153,6 +153,7 @@ pos_semihosting_call:
#if defined(ARCHI_HAS_CLUSTER)
pe_start:
#if defined(ARCHI_HMR)
csrr t0, 0xf14
li t1, ARCHI_HMR_ADDR + HMR_CORE_OFFSET
andi t0, t0, 0x01f
@ -160,6 +161,7 @@ pe_start:
add t0, t0, t1
lw t1, HMR_CORE_REGS_SP_STORE_REG_OFFSET(t0)
bnez t1, pos_hmr_tmr_reload
#endif
la x2, cluster_stacks
lw x2, 0(x2)
li x3, CLUSTER_STACK_SIZE

11
kernel/hmr_synch.c
View file

@ -205,12 +205,8 @@ void __attribute__((naked)) pos_hmr_tmr_irq() {
}
void __attribute__((naked)) pos_hmr_tmr_synch() {
if (TMR_IS_MAIN_CORE(core_id())) {
eu_bar_setup(eu_bar_addr(TMR_BARRIER_ID(TMR_GROUP_ID(core_id()))), TMR_BARRIER_SETUP(TMR_GROUP_ID(core_id())));
// eu_bar_setup(eu_bar_addr(0), hmr_get_active_cores(0));
}
pos_hmr_store_state_to_stack();
// store sp to hmr core reg
__asm__ __volatile__(
"csrr t0, 0xf14 \n\t" // Read core id
@ -220,7 +216,7 @@ void __attribute__((naked)) pos_hmr_tmr_synch() {
"add t0, t0, t1 \n\t"
"sw sp, " QU(HMR_CORE_REGS_SP_STORE_REG_OFFSET) "(t0) \n\t"
: : : "memory");
// enter barrier -> this should lock the cores together
eu_bar_trig_wait_clr(eu_bar_addr(TMR_BARRIER_ID(TMR_GROUP_ID(core_id()))));
@ -240,7 +236,7 @@ int hmr_tmr_critical_section(int (*function_handle)()) {
int ret = 0;
if (TMR_IS_MAIN_CORE(core_id())) {
// enter critical section
hmr_enable_tmr(0, TMR_GROUP_ID(core_id()));
hmr_self_enable_tmr();
// do critical stuff
ret += function_handle();
@ -249,7 +245,6 @@ int hmr_tmr_critical_section(int (*function_handle)()) {
hmr_disable_tmr(0, TMR_GROUP_ID(core_id()));
}
synch_barrier();
return ret;
}