From 90a189ed48e9494efd91908cce1dedee2286e5ab Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 30 Oct 2023 22:15:17 +0100 Subject: [PATCH] Make DMR regression work on standalone PULP cluster. --- include/hal/hmr/hmr_v1.h | 5 +++++ kernel/hmr_synch.c | 11 ++++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/include/hal/hmr/hmr_v1.h b/include/hal/hmr/hmr_v1.h index c86181e..e126ef1 100644 --- a/include/hal/hmr/hmr_v1.h +++ b/include/hal/hmr/hmr_v1.h @@ -54,6 +54,11 @@ void pos_hmr_tmr_irq(); void pos_hmr_synch(); +/* Allows for setting up proper barriers depending on available cores */ +static void hmr_setup_barrier(unsigned int num_avail_cores){ + eu_bar_setup(eu_bar_addr(0), num_avail_cores); +} + static inline unsigned int hmr_get_available_config(unsigned int cid) { return pulp_read32(ARCHI_HMR_GLOBAL_ADDR(cid) + HMR_TOP_OFFSET + HMR_REGISTERS_AVAIL_CONFIG_REG_OFFSET); } diff --git a/kernel/hmr_synch.c b/kernel/hmr_synch.c index ef7e248..bdb10c6 100644 --- a/kernel/hmr_synch.c +++ b/kernel/hmr_synch.c @@ -365,11 +365,12 @@ void __attribute__((naked)) pos_hmr_synch() { "li t2, " QU(ARCHI_EU_DEMUX_ADDR + EU_BARRIER_DEMUX_OFFSET) " \n\t" // t1 is tmr base address "add t1, t1, t2 \n\t" "p.elw zero, " QU(EU_HW_BARR_TRIGGER_WAIT_CLEAR) "(t1) \n\t" // barrier - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" + /* Removing the following nops to allow the cores to continue executing */ + // "nop\n\t" + // "nop\n\t" + // "nop\n\t" + // "nop\n\t" + // "nop\n\t" "j pos_hmr_load_part_from_stack \n" // Executes mret #endif // !ARCHI_HMR_NO_RAPID_RECOVERY