Quality-of-life changes

1) export also fast_preload bootmode (for EFCL summer school)
2) remove warnings due to non-whitespace characters in archi/utils.h
3) reset all registers in CV32E40X at boot (probably not needed, but
   good practice anyways)
This commit is contained in:
Francesco Conti 2024-05-25 20:33:59 +02:00
parent 326f85ce9a
commit 7ea5a725e4
3 changed files with 37 additions and 18 deletions

View file

@ -3,6 +3,8 @@
export PULPRT_TARGET=pulpissimo
export PULPRUN_TARGET=pulpissimo
export USE_CV32E40X=1
export CONFIG_PLUSARG_SIM=1
export bootmode=fast_debug
if [ -n "${ZSH_VERSION:-}" ]; then
DIR="$(readlink -f -- "${(%):-%x}")"

View file

@ -20,10 +20,10 @@
#define __ARCHI_DEF_REG_STR(x) #x
#define _ARCHI_DEF_REG_MASK(x) __ARCHI_DEF_REG_STR(x ## _MASK ARCHI_REG_MASK(x ## _BIT, x ## _BITS))
#define _ARCHI_DEF_REG_MASK(x) __ARCHI_DEF_REG_STR(x ## _MASK ARCHI_REG_MASK(x ## _BIT, x ## _BITS))
#define ARCHI_DEF_REG_MASK(x) _ARCHI_DEF_REF_MASK(x)
#define _ARCHI_DEF_REG_VALUE(x, vname, val) __ARCHI_DEF_REG_STR(x ## _ ## vname (val << (x ## _BIT)))
#define _ARCHI_DEF_REG_VALUE(x, vname, val) __ARCHI_DEF_REG_STR(x ## _ ## vname (val << (x ## _BIT)))
#define ARCHI_DEF_REG_VALUE(x, vname, val) _ARCHI_DEF_REG_VALUE(x, vname, val)

View file

@ -21,24 +21,41 @@
.global pos_init_entry
pos_init_entry:
# clear all register values (for latch-based regfiles)
li ra, 0
li sp, 0
li gp, 0
li tp, 0
li t0, 0
li t1, 0
li t2, 0
li s0, 0
li s1, 0
li a0, 0
li a1, 0
li a2, 0
li a3, 0
li a4, 0
li a5, 0
li a6, 0
li a7, 0
li s2, 0
li s3, 0
li s4, 0
li s5, 0
li s6, 0
li s7, 0
li s8, 0
li s9, 0
li s10, 0
li s11, 0
li t3, 0
li t4, 0
li t5, 0
li t6, 0
# Cluster PEs will also starts here to avoid aligning another entry point
# Just re-route them to the right entry
xor ra, ra, ra
xor t0, t0, t0
xor t1, t1, t1
xor t2, t2, t2
xor t3, t3, t3
xor t4, t4, t4
xor t5, t5, t5
xor t6, t6, t6
xor a0, a0, a0
xor a1, a1, a1
xor a2, a2, a2
xor a3, a3, a3
xor a4, a4, a4
xor a5, a5, a5
xor a6, a6, a6
xor a7, a7, a7
#if defined(ARCHI_HAS_CLUSTER)
csrr a0, 0xF14